JODY-W2 - System integration manual
UBX-18068879 - R14
Design-in
Page 30 of 84
C1 - Public
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One exception is represented by High Impedance traces (such as signals driven by weak pull
resistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4w
from other busses is recommended.
General considerations for schematic design and PCB floor-planning
•
Verify which signal bus requires termination and add series resistor terminations to the
schematics.
•
Carefully consider the placement of the module with respect to antenna position and host
processor; RF trace length should be minimized first, followed by SDIO bus length.
•
SDIO bus routing shall be planned to minimize layer-to-layer transition to a minimum.
•
Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning for
antenna traces and busses.
•
Verify that the power supply design and power sequence are compliant with JODY-W2
specification described in
System function interfaces
.
Component placement
•
Accessory parts like bypass capacitors should be placed as close as possible to the module to
improve filtering capability, prioritizing the placement of the smallest size capacitor close to
module pins.
•
Take care not to place components close to the antenna area. The designer should carefully follow
the recommendations from the antenna manufacturer about the distance of the antenna vs.
other parts of the system. The designer should also maximize the distance of the antenna to Hi-
frequency busses like DDRs and related components or consider an optional metal shield to reduce
interferences that could be picked up by the antenna thus reducing the module’s sensitivity.
Layout and manufacturing
•
Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB
trace.
•
Verify the recommended maximum signal skew for differential pairs and length matching of buses.
•
Minimize the routing length; longer traces will degrade signal performance. Ensure that maximum
allowable length for high-speed busses is not exceeded.
•
Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for
proper stack-up definition.
•
RF, analog and digital sections should have dedicated and clearly separated areas on the board.
•
No digital routing is allowed in the GND reference plane area of RF traces (ANT pin and Antenna).
•
It is strongly recommended to avoid digital routing beneath all layers of RF traces.
•
Ground cuts or separation are not allowed below the module.
•
Minimize the length of the RF traces, and then minimize the bus length to reduce potential EMI
issues from digital busses.
•
All traces (including low speed or DC traces) must couple with a reference plane (GND or power),
Hi-speed busses should be referenced to the ground plane. In this case, if the designer needs to
change the ground reference, an adequate number of GND vias must be added in the area of
transition to provide a low impedance path between the two GND layers for the return current.
•
Hi-Speed busses are not allowed to change reference plane. If a reference plane change is
unavoidable, some capacitors should be added in the area to provide a low impedance return path
through the different reference planes.
•
Trace routing should keep a distance greater than 3w from the ground plane routing edge.
•
Power planes should keep a distance from the PCB edge sufficient to route a ground ring around
the PCB, the ground ring must then be connected to other layers through vias.
