Toshiba TMPM4K Reference Manual Download

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TMPM4K Group(1)

Product Inromation

2018-09-18

8 / 89

Rev. 2.1

Conventions

Numeric formats follow the rules as shown below:

Hexadecimal: 0xABC
Decimal:

123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.

Binary:

0b111 – It is possible to omit the "0b" when the number of bit can be distinctly

understood from a sentence.

"_N" is added to the end of signal names to indicate low active signals.

It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.

When two or more signal names are referred, they are described like as [m: n].

Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.

The characters surrounded by

[ ]

defines the register.

Example:

[ABCD]

"n" substitutes suffix number of two or more same kind of registers, fields, and bit names.

Example:

[XYZ1]

[XYZ2]

[XYZ3]



[XYZn]

"x" substitutes suffix number or character of units and channels in the Register List.

In case of unit, "x" means A, B, and C ...
Example:

[ADACR0]

[ADBCR0]

[ADCCR0]



[ADxCR0]

In case of channel, "x" means 0, 1, and 2 ...
Example:

[T32A0RUNA]

[T32A1RUNA]

[T32A2RUNA]



[T32AxRUNA]

The bit range of a register is written like as [m: n].

Example: Bit[3: 0] expresses the range of bit 3 to 0.

The configuration value of a register is expressed by either the hexadecimal number or the binary number.

Example:

[ABCD]

<EFG> =0x01 (hexadecimal),

[XYZn]

<VW> =1 (binary)

Word and Byte represent the following bit length.

Byte:

8 bits

Half word:

16 bits

Word:

32 bits

Double word: 64 bits

Properties of each bit in a register are expressed as follows:

Read only

Write only

R/W:

Read and Write are possible

Unless otherwise specified, register access supports only word access.

The register defined as reserved must not be rewritten. Moreover, do not use the read value.

The value read from the bit having default value of "-" is unknown.

When a register containing both of writable bits and read-only bits is written, read-only bits should be

written with their default value, In the cases that default is "-", follow the definition of each register.

Reserved bits of the Write-only register should be written with their default value.

In the cases that default is "-", follow the definition of each register.

Do not use read-modified-write processing to the register of a definition which is different by writing and

read out.

Summary of Contents for TMPM4K

Page 1: ...1 Product Inromation 2018 09 18 1 89 Rev 2 1 2017 2018 Toshiba Electronic Devices Storage Corporation 2018 09 32 bit RISC Microcontroller TMPM4K Group 1 Reference Manual Product Information PINFO M4K 1 Revision 2 1 ...

Page 2: ...ontrol Register 6 32 2 2 4 8 TSELxCR7 Control Register 7 34 2 2 4 9 TSELxCR8 Control Register 8 36 2 2 4 10 TSELxCR9 Control Register 9 38 2 2 4 11 TSELxCR10 Control Register 10 40 Direct Memory Access Controller 41 2 3 1 Built in unit 41 2 3 2 DMA Request Table 41 32 bit Timer Event Counter T32A 45 2 4 1 Built in channel 45 2 4 2 Functional pins 46 2 4 3 Clock for prescaler 48 2 4 4 Internal sign...

Page 3: ...2 bit Analog to Digital Converter ADC 66 2 8 1 Built in unit 66 2 8 2 Function pin and port 66 2 8 3 Conversion clock of ADC 67 2 8 4 Startup trigger 67 2 8 5 DMA request 68 2 8 6 Other connection 68 Advanced Programmable Motor Control Circuit A PMD 69 2 9 1 Built in channel 69 2 9 2 Function pin and port 69 2 9 3 DMA request 70 2 9 4 Internal signal connection specification 71 2 9 4 1 Other conne...

Page 4: ...nterface List for each product 80 Non Break Debug Interface NBDIF 81 2 18 1 Correspondence table 81 2 18 2 NBDIF List for each product 81 Digital Noise Filter DNF 82 2 19 1 Built in unit 82 2 19 2 External Interrupt list for the each product 82 2 19 3 Sampling source clock 83 Trimming Circuit TRM 83 2 20 1 Support products 83 2 20 2 Target oscillator 83 Voltage Detection Circuit LVD 84 2 21 1 Supp...

Page 5: ... for each product 53 Table 2 21 T32A DMA request 1 2 54 Table 2 22 T32A DMA request 2 2 55 Table 2 23 UART built in channel 56 Table 2 24 UART functional pin and port 56 Table 2 25 UART Clock for prescaler 57 Table 2 26 UART DMA request 57 Table 2 27 UART trigger transfer signal connection 58 Table 2 28 UART inside connection list output 59 Table 2 29 TSPI built in channel 60 Table 2 30 TSPI funct...

Page 6: ...ble 2 64 SIWDT count clock 77 Table 2 65 SIWDT output control 77 Table 2 66 CRC built in channel 78 Table 2 67 RAMP built in channel 78 Table 2 68 RAM area and address of RAMP 78 Table 2 69 OFD support product 79 Table 2 70 OFD reference clock 79 Table 2 71 OFD clock for detection 79 Table 2 72 Debug interface List 80 Table 2 73 NBDIF correspondence table 81 Table 2 74 NBDIF interface List 81 Tabl...

Page 7: ...RT C Serial Peripheral Interface TSPI B I2C interface I2C B 12 bit Analog to Digital Converter ADC B Operational Amplifier OPAMP A Advanced Programmable Motor Control Circuit A PMD A Advanced Encoder Input Circuit A ENC A Advanced Vector Engine Plus A VE B Clock Selective Watchdog Timer SIWDT A Oscillation Frequency Detector OFD A Debug Interface DEBUG A Non break debug Interface NBDIF A Digital N...

Page 8: ...A0RUNA T32A1RUNA T32A2RUNA T32AxRUNA The bit range of a register is written like as m n Example Bit 3 0 expresses the range of bit 3 to 0 The configuration value of a register is expressed by either the hexadecimal number or the binary number Example ABCD EFG 0x01 hexadecimal XYZn VW 1 binary Word and Byte represent the following bit length Byte 8 bits Half word 16 bits Word 32 bits Double word 64...

Page 9: ...rage Technology Inc Super Flash is registered trademark of Silicon Storage Technology Inc All other company names product names and service names mentioned herein may be trademarks of their respective companies Arm Cortex and Thumb are registered trademarks of Arm Limited or its subsidiaries in the US and or elsewhere All rights reserved ...

Page 10: ... Direct Memory Access Controller DNF Digital Noise Filter EHOSC External High Speed Oscillator IHOSC Internal High Speed Oscillator INT Interrupt I2C Inter Integrated Circuit LVD Voltage Detection Circuit NBDIF Non Break Debug Interface OFD Oscillation Frequency Detector OPAMP Operational Amplifier RAMP RAM parity SIWDT Clock Selective Watchdog Timer TRGSEL Trigger Selection circuit TRM Trimming c...

Page 11: ...with Reference Manual for Peripheral Function Information of Peripheral Function Register Base address The following table shows the type of base address of each peripheral Table 2 1 Type of Register base address Product Type of Base Address TMPM4K Group 1 TYPE1 To develop each peripheral function please refer to the above type of base address In case of no information of Type1 2 of the base addre...

Page 12: ...lector The setup of input trigger selection edge detection condition selection trigger output selection and trigger output control is performed by TSEL0CR3 TRGSEL Control Register 3 TSEL0CR3 INSEL13 2 0 ch6 transmission end interrupt ch7 transmission end interrupt ch14 transmission end interrupt ch15 transmission end interrupt ch21 transmission end interrupt ch25 transmission end interrupt ch27 tr...

Page 13: ...CR1 INSEL4 DMA ch22 T32A ch0 DMA request at match B1 register T32A ch1 DMA request at match B1 register T32A ch2 DMA request at match B1 register T32A ch3 DMA request at match B1 register T32A ch4 DMA request at match B1 register T32A ch5 DMA request at match B1 register INSEL5 DMA ch23 T32A ch0 DMA request at capture A0 register T32A ch0 DMA request at capture A1 register T32A ch1 DMA request at ...

Page 14: ...ompletion DMAC ch17 transfer completion DMAC ch22 transfer completion INSEL11 DMA ch29 DMAC ch2 transfer completion DMAC ch3 transfer completion DMAC ch10 transfer completion DMAC ch11 transfer completion DMAC ch18 transfer completion DMAC ch19 transfer completion DMAC ch23 transfer completion PF0 TRGIN0 TSEL0CR3 INSEL12 DMA ch30 DMAC ch4 transfer completion DMAC ch5 transfer completion DMAC ch12 ...

Page 15: ...er C1 match trigger INSEL19 UART ch0 PF0 TRGIN0 PB1 TRGIN1 PF2 TRGIN2 T32A ch5 Timer register A1 match trigger T32A ch5 Timer register B1 match trigger T32A ch5 Timer register C1 match trigger TSEL0CR5 INSEL20 UART ch1 PF0 TRGIN0 PB1 TRGIN1 PF2 TRGIN2 T32A ch5 Timer register A1 match trigger T32A ch5 Timer register B1 match trigger T32A ch5 Timer register C1 match trigger INSEL21 UART ch2 PF0 TRGI...

Page 16: ...SPI ch1 receive completion INSEL27 T32A ch1 Timer B T32A ch1 Timer register A0 match trigger T32A ch1 Timer register A1 match trigger T32A ch1 Timer A overflow trigger T32A ch1 Timer A underflow trigger TSEL0CR7 INSEL28 T32A ch1 Timer C T32A ch0 Timer register C0 match trigger T32A ch0 Timer register C1 match trigger T32A ch0 Timer C overflow trigger T32A ch0 Timer C underflow trigger INSEL29 T32A...

Page 17: ... TRGIN0 PB1 TRGIN1 PF2 TRGIN2 A ENC ch0 divided pulse signal TSEL0CR9 INSEL36 T32A ch4 Timer B T32A ch4 Timer register A0 match trigger T32A ch4 Timer register A1 match trigger T32A ch4 Timer A overflow trigger T32A ch4 Timer A underflow trigger INSEL37 T32A ch4 Timer C T32A ch3 Timer register C0 match trigger T32A ch3 Timer register C1 match trigger T32A ch3 Timer C overflow trigger T32A ch3 Time...

Page 18: ...vice bit TSEL0CRn INSELm of the control register n register number m trigger number 2 Selection of edge detection conditions TSEL0CRn UPDNm For the input trigger signal which needs edge detection selection of rising edge or falling edge detection is performed Please set up selection of edge detection conditions in the selection bit TSEL0CRn UPDNm of a control register The following shows the trigg...

Page 19: ...00BB800 Register name Address Base Control Register 0 TSELxCR0 0x0000 Control Register 1 TSELxCR1 0x0004 Control Register 2 TSELxCR2 0x0008 Control Register 3 TSELxCR3 0x000C Control Register 4 TSELxCR4 0x0010 Control Register 5 TSELxCR5 0x0014 Control Register 6 TSELxCR6 0x0018 Control Register 7 TSELxCR7 0x001C Control Register 8 TSELxCR8 0x0020 Control Register 9 TSELxCR9 0x0024 Control Registe...

Page 20: ...UPDN3 0 R W Edge detection 0 Rising edge detection 1 falling edge detection 25 OUTSEL3 0 R W Select the output trigger 0 The edge detection is disable 1 The edge detection is enable 24 EN3 0 R W Trigger output control 0 Disable 1 Enable 23 0 R Read as 0 22 20 INSEL2 2 0 000 R W Select the input trigger DMA ch20 000 T32A ch2 DMA request at match A1 register T32A02DMAREQCMPA1 001 T32A ch2 DMA reques...

Page 21: ... detection 1 Falling edge detection 9 OUTSEL1 0 R W Select the output trigger 0 The edge detection is disable 1 The edge detection is enable 8 EN1 0 R W Trigger output control 0 Disable 1 Enable 7 0 R Read as 0 6 4 INSEL0 2 0 000 R W Select the input trigger DMA ch18 000 ADC general purpose trigger DMA request ADATRG_DMAREQ 001 ADC single conversion DMA request ADASGL_DMAREQ 010 ADC continuous con...

Page 22: ... T32A ch2 DMA request capture A1 T32A02DMAREQCAPA1 010 T32A ch3 DMA request capture A0 T32A03DMAREQCAPA0 011 T32A ch3 DMA request capture A1 T32A03DMAREQCAPA1 100 T32A ch2 DMA request capture C0 T32A02DMAREQCAPC0 101 T32A ch2 DMA request capture C1 T32A02DMAREQCAPC1 110 T32A ch3 DMA request capture C0 T32A03DMAREQCAPC0 111 T32A ch3 DMA request capture C1 T32A03DMAREQCAPC1 19 0 R Read as 0 18 UPDN6...

Page 23: ...001 T32A ch1 DMA request at match B1 register T32A01DMAREQCMPB1 010 T32A ch2 DMA request at match B1 register T32A02DMAREQCMPB1 011 T32A ch3 DMA request at match B1 register T32A03DMAREQCMPB1 100 T32A ch4 DMA request at match B1 register T32A04DMAREQCMPB1 101 T32A ch5 DMA request at match B1 register T32A05DMAREQCMPB1 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN4 0 R W Edge detection 0 Rising ...

Page 24: ...0 transfer completion INTDMAATC0 001 DMAC ch1 transfer completion INTDMAATC1 010 DMAC ch8 transfer completion INTDMAATC8 011 DMAC ch9 transfer completion INTDMAATC9 100 DMAC ch16 transfer completion INTDMAATC16 101 DMAC ch17 transfer completion INTDMAATC17 110 DMAC ch22 transfer completion INTDMAATC22 111 Reserved 19 0 R Read as 0 18 UPDN10 0 R W Edge detection 0 Rising edge detection 1 Falling ed...

Page 25: ...0 T32A00DMAREQCAPB0 001 T32A ch0 DMA request capture B1 T32A00DMAREQCAPB1 010 T32A ch1 DMA request capture B0 T32A01DMAREQCAPB0 011 T32A ch1 DMA request capture B1 T32A01DMAREQCAPB1 100 T32A ch2 DMA request capture B0 T32A00DMAREQCAPB0 101 T32A ch2 DMA request capture B1 T32A01DMAREQCAPB1 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN8 0 R W Edge detection 0 Rising edge detection 1 Falling edge ...

Page 26: ... trigger 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 T32A ch5 Timer register A1 match trigger T32A05TRGOUTCMPA1 100 T32A ch5 Timer register B1 match trigger T32A05TRGOUTCMPB1 101 T32A ch5 Timer register C1 match trigger T32A05TRGOUTCMPC1 110 Reserved 111 Reserved 19 0 R Read as 0 18 UPDN14 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 17 OUTSEL14 0 R W Select the outpu...

Page 27: ...letion INTDMAATC4 001 DMAC ch5 transfer completion INTDMAATC5 010 DMAC ch12 transfer completion INTDMAATC12 011 DMAC ch13 transfer completion INTDMAATC13 100 DMAC ch20 transfer completion INTDMAATC20 101 DMAC ch24 transfer completion INTDMAATC24 110 DMAC ch26 transfer completion INTDMAATC26 111 PB1 TRGIN1 3 0 R Read as 0 2 UPDN12 0 R W Edge detection 0 Rising edge detection 1 Falling edge detectio...

Page 28: ...nput trigger TSPI ch3 trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 T32A ch5 Timer register A1 match trigger T32A05TRGOUTCMPA1 100 T32A ch5 Timer register B1 match trigger T32A05TRGOUTCMPB1 101 T32A ch5 Timer register C1 match trigger T32A05TRGOUTCMPC1 110 Reserved 111 Reserved 19 0 R Read as 0 18 UPDN18 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 17 OUTS...

Page 29: ...ch1 trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 T32A ch5 Timer register A1 match trigger T32A05TRGOUTCMPA1 100 T32A ch5 Timer register B1 match trigger T32A05TRGOUTCMPB1 101 T32A ch5 Timer register C1 match trigger T32A05TRGOUTCMPC1 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN16 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUTSEL16 0 R W Select the...

Page 30: ... the input trigger UART ch3 trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 T32A ch5 Timer register A1 match trigger T32A05TRGOUTCMPA1 100 T32A ch5 Timer register B1 match trigger T32A05TRGOUTCMPB1 101 T32A ch5 Timer register C1 match trigger T32A05TRGOUTCMPC1 110 Reserved 111 Reserved 19 0 R Read as 0 18 UPDN22 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1...

Page 31: ...ch1 trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 T32A ch5 Timer register A1 match trigger T32A05TRGOUTCMPA1 100 T32A ch5 Timer register B1 match trigger T32A05TRGOUTCMPB1 101 T32A ch5 Timer register C1 match trigger T32A05TRGOUTCMPC1 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN20 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUTSEL20 0 R W Select the...

Page 32: ...trigger T32A ch1 Timer A internal trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 UART ch1 transmission completion trigger UART1TXTRG 100 UART ch1 reception completion trigger UART1RXTRG 101 TSPI ch1 transmit completion TSPI1TXEND 110 TSPI ch1 receive completion TSPI1RXEND 111 Reserved 19 0 R Read as 0 18 UPDN26 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1...

Page 33: ...rigger input 000 T32A ch0 Timer register A0 match trigger T32A00TRGOUTCMPA0 001 T32A ch0 Timer register A1 match trigger T32A00TRGOUTCMPA1 010 T32A ch0 Timer A overflow trigger T32A00TRGOUTOFA 011 T32A ch0 Timer A underflow trigger T32A00TRGOUTUFA 100 Reserved 101 Reserved 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN24 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUT...

Page 34: ...trigger T32A ch2 Timer B internal trigger input 000 T32A ch2 Timer register A0 match trigger T32A02TRGOUTCMPA0 001 T32A ch2 Timer register A1 match trigger T32A02TRGOUTCMPA1 010 T32A ch2 Timer A overflow trigger T32A02TRGOUTOFA 011 T32A ch2 Timer A underflow trigger T32A02TRGOUTUFA 100 Reserved 101 Reserved 110 Reserved 111 Reserved 19 0 R Read as 0 18 UPDN30 0 R W Edge detection 0 Rising edge det...

Page 35: ...rigger input 000 T32A ch0 Timer register C0 match trigger T32A00TRGOUTCMPC0 001 T32A ch0 Timer register C1 match trigger T32A00TRGOUTCMPC1 010 T32A ch0 Timer C overflow trigger T32A00TRGOUTOFC 011 T32A ch0 Timer C underflow trigger T32A00TRGOUTUFC 100 Reserved 101 Reserved 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN28 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUT...

Page 36: ...ger T32A02TRGOUTCMPC0 001 T32A ch2 Timer register C1 match trigger T32A02TRGOUTCMPC1 010 T32A ch2 Timer C overflow trigger T32A02TRGOUTOFC 011 T32A ch2 Timer C underflow trigger T32A02TRGOUTUFC 100 Reserved 101 Reserved 110 Reserved 111 Reserved 19 0 R Read as 0 18 UPDN34 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 17 OUTSEL34 0 R W Select the output trigger 0 The edge de...

Page 37: ...nal trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 UART ch3 transmission completion trigger UART3TXTRG 100 UART ch3 reception completion trigger UART3RXTRG 101 TSPI ch3 transmit completion TSPI3TXEND 110 TSPI ch3 receive completion TSPI3RXEND 111 I2 C ch0 I2 C interrupt INTI2C0 3 0 R Read as 0 2 UPDN32 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUTSEL32...

Page 38: ... Timer A internal trigger input 000 PF0 TRGIN0 001 PB1 TRGIN1 010 PF2 TRGIN2 011 ADC general purpose trigger interrupt INTADATRG 100 ADC single conversion interrupt INTADASGL 101 ADC continuous conversion interrupt INTADACNT 110 ADC monitor function 0 Interrupt INTADACP0 111 ADC monitor function 1 Interrupt INTADACP1 19 0 R Read as 0 18 UPDN38 0 R W Edge detection 0 Rising edge detection 1 Falling...

Page 39: ...rigger input 000 T32A ch4 Timer register A0 match trigger T32A04TRGOUTCMPA0 001 T32A ch4 Timer register A1 match trigger T32A04TRGOUTCMPA1 010 T32A ch4 Timer A overflow trigger T32A04TRGOUTOFA 011 T32A ch4 Timer A underflow trigger T32A04TRGOUTUFA 100 Reserved 101 Reserved 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN36 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUT...

Page 40: ...2A04TRGOUTCMPC0 001 T32A ch4 Timer register C1 match trigger T32A04TRGOUTCMPC1 010 T32A ch4 Timer C overflow trigger T32A04TRGOUTOFC 011 T32A ch4 Timer C underflow trigger T32A04TRGOUTUFC 100 Reserved 101 Reserved 110 Reserved 111 Reserved 3 0 R Read as 0 2 UPDN40 0 R W Edge detection 0 Rising edge detection 1 Falling edge detection 1 OUTSEL40 0 R W Select the output trigger 0 The edge detection i...

Page 41: ...MA TSPI ch1 transmission TSPI1TX_DMA 4 TSPI ch2 reception TSPI2RX_DMA TSPI ch2 reception TSPI2RX_DMA 5 TSPI ch2 transmission TSPI2TX_DMA TSPI ch2 transmission TSPI2TX_DMA 6 TSPI ch3 reception TSPI3RX_DMA TSPI ch3 reception TSPI3RX_DMA 7 TSPI ch3 transmission TSPI3TX_DMA TSPI ch3 transmission TSPI3TX_DMA 8 UART ch0 reception UART0RX_DMAREQ UART ch0 reception UART0RX_DMAREQ 9 UART ch0 transmission U...

Page 42: ...QCMPC1 T32A ch5 compare A1 matched T32A05DMAREQCMPA1 T32A ch5 compare C1 matched T32A05DMAREQCMPC1 22 TSEL0CR1 INSEL4 T32A ch0 capture B1 T32A00DMAREQCAPB1 T32A ch1 capture B1 T32A00DMAREQCAPB1 T32A ch2 capture B1 T32A01DMAREQCAPB1 T32A ch3 capture B1 T32A01DMAREQCAPB1 T32A ch4 capture B1 T32A00DMAREQCAPB1 T32A ch5 capture B1 T32A00DMAREQCAPB1 23 TSEL0CR1 INSEL5 T32A ch0 capture A0 T32A00DMAREQCAP...

Page 43: ...ture B0 T32A03DMAREQCAPB0 T32A ch3 capture B1 T32A03DMAREQCAPB1 T32A ch4 capture B0 T32A04DMAREQCAPB0 T32A ch4 capture B1 T32A04DMAREQCAPB1 T32A ch5 capture B0 T32A05DMAREQCAPB0 T32A ch5 capture B1 T32A05DMAREQCAPB1 28 TSEL0CR2 INSEL10 DMAC ch0 transfer completion INTDMAATC0 DMAC ch1 transfer completion INTDMAATC1 DMAC ch8 transfer completion INTDMAATC8 DMAC ch9 transfer completion INTDMAATC9 DMAC...

Page 44: ...pletion INTDMAATC20 DMAC ch24 transfer completion INTDMAATC24 DMAC ch26 transfer completion INTDMAATC26 TRGIN1 PB1 TRGIN1 31 TSEL0CR3 INSEL13 DMAC ch6 transfer completion INTDMAATC6 DMAC ch7 transfer completion INTDMAATC7 DMAC ch14 transfer completion INTDMAATC14 DMAC ch15 transfer completion INTDMAATC15 DMAC ch21 transfer completion INTDMAATC21 DMAC ch25 transfer completion INTDMAATC25 DMAC ch27 ...

Page 45: ... 45 89 Rev 2 1 32 bit Timer Event Counter T32A 2 4 1 Built in channel Following table shows the T32A built in channel of each product Table 2 12 T32A built in channel Product T32A channel Available N A ch0 ch1 ch2 ch3 ch4 ch5 M4K4 M4K2 M4K1 M4K0 ...

Page 46: ...t Ports for products Available N A M4K4 M4K2 M4K1 M4K0 ch0 T32A00INA0 Input PK1 T32A00INA1 Input T32A00OUTA Output PK0 T32A00INB0 Input T32A00INB1 Input T32A00OUTB Output T32A00INC0 Input PK1 T32A00INC1 Input T32A00OUTC Output PK0 ch1 T32A01INA0 Input PA1 T32A01INA1 Input PA2 T32A01OUTA Output PA2 T32A01INB0 Input PA0 T32A01INB1 Input T32A01OUTB Output PA0 T32A01INC0 Input PA1 T32A01INC1 Input PA2...

Page 47: ...INB0 Input T32A03INB1 Input T32A03OUTB Output T32A03INC0 Input PC1 T32A03INC1 Input PC2 T32A03OUTC Output PC0 ch4 T32A04INA0 Input PF1 T32A04INA1 Input PF2 T32A04OUTA Output PF0 T32A04INB0 Input T32A04INB1 Input T32A04OUTB Output T32A04INC0 Input PF1 T32A04INC1 Input PF2 T32A04OUTC Output PF0 ch5 T32A05INA0 Input PB1 T32A05INA1 Input T32A05OUTA Output PB0 T32A05INB0 Input T32A05INB1 Input T32A05OU...

Page 48: ...2A clock for prescaler Clock ΦT0 2 4 4 Internal signal connection specification 2 4 4 1 Capture trigger signal connection In the 32 bit timer event counter capture trigger signal is connected to signals of the following table The input trigger signal which has a register name in the trigger selector column of the following table should choose the input trigger used by a trigger selector ...

Page 49: ...1 match trigger T32A05TRGOUTCMPC1 T32A ch5 timer C overflow trigger T32A05TRGOUTOFC T32A ch5 timer C underflow trigger T32A05TRGOUTUFC ch1 Timer A T32A01TRGINAPHCK Other timer output T32A01TRGINAPCK Internal trigger input TSEL0CR6 INSEL26 PF0 TRGIN0 TRGIN0 PB1 TRGIN1 TRGIN1 PF2 TRGIN2 TRGIN2 UART ch1 transmission completion trigger UART1TXTRG UART ch1 reception completion trigger UART1RXTRG TSPI c...

Page 50: ...r T32A01TRGOUTCMPC1 T32A ch1 timer C overflow trigger T32A01TRGOUTOFC T32A ch1 timer C underflow trigger T32A01TRGOUTUFC ch3 Timer A T32A03TRGINAPHCK Other timer output T32A03TRGINAPCK Internal trigger input TSEL0CR8 INSEL32 PF0 TRGIN0 TRGIN0 PB1 TRGIN1 TRGIN1 PF2 TRGIN2 TRGIN2 UART ch3 transmission completion trigger UART3TXTRG UART ch3 reception completion trigger UART3RXTRG TSPI ch3 transmit co...

Page 51: ...3 timer C underflow trigger T32A03TRGOUTUFC ch5 Timer A T32A05TRGINAPHCK Other timer output T32A05TRGINAPCK Internal trigger input TSEL0CR9 INSEL38 PF0 TRGIN0 TRGIN0 PB1 TRGIN1 TRGIN1 PF2 TRGIN2 TRGIN2 ADC general purpose trigger interrupt INTADATRG ADC single conversion interrupt INTADASGL ADC continuous conversion interrupt INTADACNT ADC monitor function 0 interrupt INTADACP0 ADC monitor functio...

Page 52: ...oad B T32A01SYNCRELOADB ch2 Timer A Synchronous start output A T32A02SYNCSTARTOUTA Timer B Synchronous start B T32A02SYNCSTARTB Synchronous stop output A T32A02SYNCSTOPOUTA Synchronous stop B T32A02SYNCSTOPB Synchronous Reload output A T32A02SYNCRELOADOUTA Synchronous Reload B T32A02SYNCRELOADB ch3 Timer A Synchronous start output A T32A03SYNCSTARTOUTA Timer B Synchronous start B T32A03SYNCSTARTB ...

Page 53: ...spondence of a pulse counter changes with products Table 2 20 T32A Pulse counter list for each product Channel M4K4 M4K2 M4K1 M4K0 ch0 1 phase pulse count ch1 2 phase pulse count 1 phase pulse count 1 phase pulse count ch2 2 phase pulse count 1 phase pulse count ch3 2 phase pulse count 1 phase pulse count ch4 2 phase pulse count 1 phase pulse count ch5 1 phase pulse count ...

Page 54: ...SEL0CR1 INSEL5 23 DMA request at capture A1 register T32A00DMAREQCAPA1 DMA request at capture C0 register T32A00DMAREQCAPC0 DMA request at capture C1 register T32A00DMAREQCAPC1 DMA request at capture B0 register T32A00DMAREQCAPB0 TSEL0CR2 INSEL8 26 DMA request at capture B1 register T32A00DMAREQCAPB1 ch1 DMA request at match A1 register T32A01DMAREQCMPA1 TSEL0CR0 INSEL1 19 DMA request at match C1 ...

Page 55: ...A request at capture B0 register T32A03DMAREQCAPB0 TSEL0CR2 INSEL9 27 DMA request at capture B1 register T32A03DMAREQCAPB1 ch4 DMA request at match A1 register T32A04DMAREQCMPA1 TSEL0CR0 INSEL3 21 DMA request at match C1 register T32A04DMAREQCMPC1 DMA request at match B1 register T32A04DMAREQCMPB1 TSEL0CR1 INSEL4 22 DMA request at capture A0 register T32A04DMAREQCAPA0 TSEL0CR2 INSEL7 25 DMA reques...

Page 56: ...on pin and port The functional pins are assigned to the port of the following tables Please do not use simultaneously the same function currently assigned to two or more pins There is also a channel which does not have functional pins depending on a product Table 2 24 UART functional pin and port Channel Function Pin signal name Port Products list Available N A M4K4 M4K2 M4K1 M4K0 ch0 UT0TXDA Outp...

Page 57: ... DMA request in the UART in the table does not have an applicable function Table 2 26 UART DMA request Channel Request Signal Name Trigger selector DMA request channel Single transfer Burst transfer ch0 UART ch0 reception UART0RX_DMAREQ 8 UART ch0 transmission UART0TX_DMAREQ 9 ch1 UART ch1 reception UART1RX_DMAREQ 10 UART ch1 transmission UART1TX_DMAREQ 11 ch2 UART ch2 reception UART2RX_DMAREQ 12 ...

Page 58: ...CR5 INSEL20 PF0 TRGIN0 TRGIN0 PB1 TRGIN1 TRGIN1 PF2 TRGIN2 TRGIN2 T32A ch5 timer register A1 match trigger T32A05TRGOUTCMPA1 T32A ch5 timer register B1 match trigger T32A05TRGOUTCMPB1 T32A ch5 timer register C1 match trigger T32A05TRGOUTCMPC1 ch2 UART2TRGIN TSEL0CR5 INSEL21 PF0 TRGIN0 TRGIN0 PB1 TRGIN1 TRGIN1 PF2 TRGIN2 TRGIN2 T32A ch5 timer register A1 match trigger T32A05TRGOUTCMPA1 T32A ch5 tim...

Page 59: ...L0CR5 INSEL23 T32A ch0 Timer A T32A00TRGINAPCK UART ch0 reception completion trigger output UART0RXTRG ch1 UART ch1 transmission completion trigger output UART1TXTRG TSEL0CR6 INSEL26 T32A ch1 Timer A T32A01TRGINAPCK UART ch1 reception completion trigger output UART1RXTRG ch2 UART ch2 transmission completion trigger output UART2TXTRG TSEL0CR7 INSEL29 T32A ch2 Timer A T32A02TRGINAPCK UART ch2 recept...

Page 60: ...e following tables Please do not use simultaneously the same function currently assigned to two or more pins There is also a channel which does not have functional pins depending on a product Table 2 30 TSPI function functional pin and port Channel function pin signal name Port Products list Available N A M4K4 M4K2 M4K1 M4K0 ch0 TSPI0SCK I O PK4 TSPI0TXD Output PK3 TSPI0RXD Input PK2 ch1 TSPI1SCK ...

Page 61: ...t Mode M4K4 M4K2 M4K1 M4K0 ch0 SIO mode ch1 SIO mode ch2 SIO mode ch3 SIO mode 2 6 4 TSPIxCR2 RXDLY set value For the setting value of TSPI control register 2 TSPIxCR2 RXDLY set the values in the following table Table 2 32 TSPI TSPIxCR2 RXDLY set value Register name Value TSPIxCR2 RXDLY 1 fsys 40MHz 2 6 5 Clock for Prescaler The TSPI use the clock of the following table as a prescaler clock Table ...

Page 62: ...TRGIN2 Note2 TRGIN2 T32A ch5 timer register A1 match trigger T32A05TRGOUTCMPA1 T32A ch5 timer register B1 match trigger T32A05TRGOUTCMPB1 T32A ch5 timer register C1 match trigger T32A05TRGOUTCMPC1 ch2 TSPI2TRG input TSEL0CR4 INSEL17 PF0 TRGIN0 Note2 TRGIN0 PB1 TRGIN1 Note2 TRGIN1 PF2 TRGIN2 Note2 TRGIN2 T32A ch5 timer register A1 match trigger T32A05TRGOUTCMPA1 T32A ch5 timer register B1 match tri...

Page 63: ...ch2 transmission completion TSPI2TXEND TSEL0CR7 INSEL29 T32A ch2 Timer A T32A02TRGINAPCK TSPI ch2 reception completion TSPI2RXEND ch3 TSPI ch3 transmission completion TSPI3TXEND TSEL0CR8 INSEL32 T32A ch3 Timer A T32A03TRGINAPCK TSPI ch3 reception completion TSPI3RXEND 2 6 7 DMA request The following table shows the DMA request in the TSPI in the table does not have an applicable function Table 2 3...

Page 64: ... channel Product I2 C channel Available N A ch0 M4K4 M4K2 M4K1 M4K0 2 7 2 Function pin and port The functional pins are assigned to the port of the following tables Table 2 38 I2C interface function pin and port Channel Function pin signal name Port Product list Available N A M4K4 M4K2 M4K1 M4K0 ch0 I2C0SCL I O PB1 I2C0SDA I O PB0 2 7 3 Clock for Prescaler The I2 C use the clock of the following t...

Page 65: ...he DMA request in the I2 C in the table does not have an applicable function Table 2 40 I2 C interface DMA request Channel Request Signal name Trigger selector DMA request channel Single transfer Burst transfer ch0 I2 C ch0 reception I2C0RXDMAREQ 16 I2 C ch0 transmission I2C0TXDMAREQ 17 Note Available N A ...

Page 66: ...epending on a product Table 2 42 ADC function pin and port Input channel Function pin signal name Port Product list Available N A M4K4 M4K2 M4K1 M4K0 ch0 AINA00 PD0 ch1 AINA01 PD1 ch2 ch3 AINA03 PD2 ch4 AINA04 PD3 ch5 ch6 AINA06 PD4 ch7 AINA07 PD5 ch8 ch9 AINA09 PD6 ch10 AINA10 PE0 ch11 AINA11 PE1 ch12 AINA12 PE2 ch13 AINA13 PE3 ch14 AINA14 PE4 ch15 AINA15 VREFH PE5 ch16 AVDD5 Note2 ch17 VREFL Not...

Page 67: ...e PMD0TRG0 A PMD ch0 trigger 0 PMD0TRG0 PMD0TRG1 A PMD ch0 trigger 1 PMD0TRG1 PMD0TRG2 A PMD ch0 trigger 2 PMD0TRG2 PMD0TRG3 A PMD ch0 trigger 3 PMD0TRG3 PMD0TRG4 A PMD ch0 trigger 4 PMD0TRG4 PMD0TRG5 A PMD ch0 trigger 5 PMD0TRG5 PMD1TRG0 A PMD ch1 trigger 0 PMD1TRG0 PMD1TRG1 A PMD ch1 trigger 1 PMD1TRG1 PMD1TRG2 A PMD ch1 trigger 2 PMD1TRG2 PMD1TRG3 A PMD ch1 trigger 3 PMD1TRG3 PMD1TRG4 A PMD ch1...

Page 68: ...ion output Trigger selector Output destination Signal name Signal name A General purpose trigger interrupt INTADATRG TSEL0CR9 INSEL38 T32A ch5 Timer A Single conversion interrupt INTADASGL Continuous conversion interrupt INTADACNT Monitor function 0 interrupt INTADACP0 Monitor function 1 interrupt INTADACP1 Monitor function 0 output for PMD protect function ADACP0L_N A PMD ch0 ADACMP0L_N A PMD ch1...

Page 69: ...nction pin and port The functional pins are assigned to the port of the following tables Table 2 48 A PMD function pin Channel Function pin Signal name Port Product list Available N A M4K4 M4K2 M4K1 M4K0 ch0 XO0 Output XO0 PJ1 YO0 Output YO0 PJ3 ZO0 Output ZO0 PJ5 UO0 Output UO0 PJ0 VO0 Output VO0 PJ2 WO0 Output WO0 PJ4 EMG0 Input EMG0 PD6 PH2 PJ6 OVV0 Input OVV0 PJ7 Debug output Output PMD0DBG PB...

Page 70: ...able shows the DMA request in the A PMD Table 2 49 A PMD DMA request Channel Request Signal name Trigger selector DMA request channel Single transfer Burst transfer ch0 A PMD ch0 PWM interrupt INTPWM0 TSEL0CR0 INSEL1 19 ch1 A PMD ch1 PWM interrupt INTPWM1 TSEL0CR0 INSEL2 20 Note Available N A ...

Page 71: ...us PMD0TMR T32A ch0 T32A00TRGOUTCMPA0 Commutation trigger A ENC MCMP completion synchronous ENC0CTRGO A ENC ENC0CTRG0 VE U phase PWM duty VE0CMPU A VE VE0CMPU VE V phase PWM duty VE0CMPV VE0CMPV VE W phase PWM duty VE0CMPW VE0CMPW VE Trigger comparison 0 VE0TRGCMP0 VE0TRGCMP0 VE Trigger comparison 1 VE0TRGCMP1 VE0TRGCMP1 VE Trigger output selection VE0TRGSEL VE0TRGSEL VE Conduction control Output ...

Page 72: ...nous trigger output 1 PMD1TRG1 PMD1TRG1 ADC synchronous trigger output 2 PMD1TRG2 PMD1TRG2 ADC synchronous trigger output 3 PMD1TRG3 PMD1TRG3 ADC synchronous trigger output 4 PMD1TRG4 PMD1TRG4 ADC synchronous trigger output 5 PMD1TRG5 PMD1TRG5 2 9 4 2 Inter channel synchronous control connection The PMD is synchronously connected between the channels as shown in the table below Table 2 52 PMD Inte...

Page 73: ...nd interrupt B INTADAPDB INTADAPDB AD conversion result 0 VADAREG0 VADAREG0 AD conversion result 1 VADAREG1 VADAREG1 AD conversion result 2 VADAREG2 VADAREG2 AD conversion result 3 VADAREG3 VADAREG3 PWM interrupt INTPWM0 A PMD ch0 INTPWM0 Table 2 55 A VE Internal connection specification Output Channel Function output Output destination Signal name Signal name ch0 U phase PWM duty VE0CMPU A PMD ch...

Page 74: ... product Table 2 56 A ENC built in channel Product A ENC channel Available N A ch0 M4K4 M4K2 M4K1 M4K0 2 11 2 Function Pin and Port The functional pins are assigned to the port of the following tables Table 2 57 A ENC function pin Channel Function Signal Name Port Product list Available N A M4K4 M4K2 M4K1 M4K0 ch0 ENC0A Input ENC0A PG0 ENC0B Input ENC0B PG1 ENC0Z Input ENC0Z PG2 ...

Page 75: ...l Signal Name ch0 General purpose timer output signal ENC0PSGI T32A ch0 Timer output A T32A00OUTA PWM signal for sampling ENC0PWMON A PMD ch0 PWM signal PMD0PWMON Table 2 59 A ENC Internal connection specification Output Channel Function output Trigger selector Output destination Signal Signal name ch0 Divided pulse signal ENC0TIMPLS TSEL0CR8 INSEL35 T32A ch4 Timer A Capture trigger input T32A04TR...

Page 76: ...onverter which can connect OPAMP is as follows Table 2 61 OPAMP connected pin OPAMP ADC pin Products Available N A M4K4 M4K2 M4K1 M4K0 AMPA AINA00 AINA01 AMPB AINA03 AINA04 AMPC AINA06 AINA07 2 12 3 Internal connection The internal connection of OPAMP and an AD converter is as follows Table 2 62 OPAMP internal connection ADC input pin OPAMP input pin OPAMP output pin OPAMP output to ADC AINA00 AIN...

Page 77: ...t The following table shows the selectable clock Table 2 64 SIWDT count clock Clock Signal Selection System clock fsys Selected by SIWD0MOD WDCLS Internal High speed oscillator1 clock fIHOSC1 Internal High speed oscillator2 clock fIHOSC2 2 13 3 Output control To select the Internal High speed oscillator 2 fIHOSC2 Rewriting of the internal High speed oscillator2 can be forbidden Table 2 65 SIWDT ou...

Page 78: ...e following table shows the RAMP built in channel of each product Table 2 67 RAMP built in channel Product RAMP built in Available N A M4K4 M4K2 M4K1 M4K0 2 15 2 Error detection block area The following table shows the detection RAM block area of each product Table 2 68 RAM area and address of RAMP Register name RAM area address Products Available N A M4K4 M4K2 M4K1 M4K0 RPARST RPARFG2 0x20002000 ...

Page 79: ...ring the clock of the following tables as a reference clock Table 2 70 OFD reference clock Reference clock Signal name Divide value Internal High speed oscillator 2 fIHOSC2 256 2 16 3 Clock for detection The Oscillation frequency detection circuit chooses the clock to monitor from the detection object clock of the following tables Table 2 71 OFD clock for detection Clock for detection Signal name ...

Page 80: ...each product Table 2 72 Debug interface List Debug function Debug Pin Signal name Port support Pin list Available N A M4K4 M4K2 M4K1 M4K0 Serial wire SWDIO PK2 SWCLK PK3 SWV PK1 JTAG TMS PK2 TCK PK3 TDO PK1 TDI PK0 TRST_N PK4 ETM trace TRACECLK PL4 TRACEDATA0 PL0 TRACEDATA1 PL1 TRACEDATA2 PL2 TRACEDATA3 PL3 ...

Page 81: ...hows the NBDIF correspondence of each product Table 2 73 NBDIF correspondence table Product Function Available N A M4K4 M4K2 M4K1 M4K0 2 18 2 NBDIF List for each product Table 2 74 NBDIF interface List Debug Pin Signal name Port Pin Available N A M4K4 M4K2 M4K1 M4K0 NBDSYNC PK4 NBDCLK PL4 NBDDATA0 PL0 NBDDATA1 PL1 NBDDATA2 PL2 NBDDATA3 PL3 ...

Page 82: ...nal interrupt pins Table 2 76 External interrupt and DNF External interrupt pin Signal name Port Setting register name DNF Available N A M4K4 M4K2 M4K1 M4K0 INT00a PK0 DNFAENCR NFEN0 INT00b PF1 DNFAENCR NFEN11 INT01a PK1 DNFAENCR NFEN1 INT01b PF2 DNFAENCR NFEN12 INT02a PK2 DNFAENCR NFEN2 INT02b PB0 DNFAENCR NFEN13 INT03a PK3 DNFAENCR NFEN3 INT03b PB1 DNFAENCR NFEN14 INT04 PG0 DNFAENCR NFEN4 INT05 ...

Page 83: ...g source clock Clock fc Trimming Circuit TRM 2 20 1 Support products The TRM is supported by the following products Table 2 78 TRM support product Product TRM support Available N A M4K4 M4K2 M4K1 M4K0 2 20 2 Target oscillator The target oscillator of the trimming circuit is the oscillator shown in the following tables Table 2 79 TRM trimming target oscillator Target oscillator Oscillator Internal ...

Page 84: ...orted by the following products Table 2 80 LVD support product Product LVD support Available N A M4K4 M4K2 M4K1 M4K0 2 21 2 Detection power supply A voltage detecting circuit monitors the power supply of the following tables Table 2 81 LVD detection power supply Detection power supply Power supply name Digital power source DVDD5 ...

Page 85: ...ock configuration of each product The code flash memory differs in the block configuration of the memory with the product as shown in the following table Table 2 83 The code flash of each product Block name M4K4FYAUG M4K4FYAFG M4K2FYADUG M4K1FYAUG M4K4FWAUG M4K4FWAFG M4K2FWADUG M4K1FWAUG M4K4FUAUG M4K4FUAFG M4K2FUADUG M4K1FUAUG M4K4FSAUG M4K4FSAFG M4K2FSADUG M4K1FSAUG M4K0FSADUG Block Size KB Bloc...

Page 86: ...9 Rev 2 1 2 22 3 Single boot resource The peripheral function of the following table is used in single boot Table 2 84 Single boot resource Peripheral function Channel Function Pin Name BOOT PJ6 BOOT_N UART ch0 RXD PK0 UT0RXD TXD PK1 UT0TXDA T32A ch0 ...

Page 87: ... 2 21 2 21 1 Support products Change section title of 2 22 128KB 256KB 2 1 2018 09 18 Conventions Revised SST registered trademarks Terms and Abbreviations NBD I F NBDIF 2 2 Trigger Selector Figure 2 1 Change input trigger Table2 2 INSEL0 general purpose trigger general purpose trigger DMA request program DMA request Table2 4 INSEL23 Table2 5 INSEL26 INSEL29 Table2 6 INSEL32 UART completion comple...

Page 88: ...gger match trigger 2 8 5 Table 2 45 Changed Cannel column to Unit column Modified name of Request column 2 8 6 Table 2 46 Changed I O column to Unit column ADC general purpose trigger General purpose trigger interrupt ADC single conversion program Single conversion interrupt ADC continuous conversion program Continuous conversion interrupt ADC monitor interrupt n Monitor function n interrupt Monit...

Page 89: ...porting medical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators and devices related to power plant IF YOU USE PRODUCT FOR UNINTENDED USE TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT For details please contact your TOSHIBA sales representative or contact...

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