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4.2 Single Phase Counter
[MWssrr Mode Select Bits = 010]
When the count input is changed from OFF to ON, the count value is increased by 1. When the count value
reaches the set value, the count value is reset to 0. This counter operation is enabled while the HSC enable
bit is ON. The count value is reset to 0 when the Reset bit is changed from OFF to ON. The count value
range is H0000 0000 to HFFFF FFFF (32-bit data).
For example, an application is given below:
1. Selects the high speed expansion model.
2. Create an application as shown in the image here.
3. Define Configuration Register. The value of this configuration register will define the mode of operation of
the high speed counter. If the configuration register value is 2, then HSC will work in single phase mode
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Summary of Contents for OIS PLUS Series
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