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2.15.3 Mailbox Interrupt Mask Register (CANMIM)
Interrupt Registers
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There is one interrupt flag available for each mailbox. This can be a receive or a transmit interrupt
depending on the configuration of the mailbox. This register is EALLOW protected.
Figure 2-19. Mailbox Interrupt Mask Register (CANMIM)
31
0
MIM.31:0
R/W-0
LEGEND: R/W = Read/Write; -
n
= value after reset
Table 2-16. Mailbox Interrupt Mask Register (CANMIM) Field Descriptions
Bit
Field
Value
Description
31:0
MIM.31:0
Mailbox interrupt mask. After power up all interrupt mask bits are cleared and the interrupts are
disabled. These bits allow any mailbox interrupt to be masked individually.
1
Mailbox interrupt is enabled. An interrupt is generated if a message has been transmitted
successfully (in case of a transmit mailbox) or if a message has been received without any error (in
case of a receive mailbox).
0
Mailbox interrupt is disabled.
eCAN Registers
50
SPRU074F – May 2002 – Revised January 2009