3.4.3 Interrupt Handling
3.4.3.1
Configuring for Interrupt Handling
Interrupts
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The CPU is interrupted by asserting one of the two interrupt lines. After handling the interrupt, which
should generally also clear the interrupt source, the interrupt flag must be cleared by the CPU. To do this,
the interrupt flag must be cleared in the CANGIF0 or CANGIF1 register. This is generally done by writing a
1 to the interrupt flag. There are some exceptions to this as stated in
. This also releases the
interrupt line if no other interrupt is pending.
Table 3-7. eCAN Interrupt Assertion/Clearing
(1)
Interrupt
GIF0/GIF1
Flag
Interrupt Condition
Determination
Clearing Mechanism
WLIFn
One or both error counters are >= 96
GIL bit
Cleared by writing a 1 to it
EPIFn
CAN module has entered “error passive”
GIL bit
Cleared by writing a 1 to it
mode
BOIFn
CAN module has entered “bus-off” mode
GIL bit
Cleared by writing a 1 to it
RMLIFn
An overflow condition has occurred in
GIL bit
Cleared by clearing the set RMPn
one of the receive mailboxes.
bit.
WUIFn
CAN module has left the local power-down
GIL bit
Cleared by writing a 1 to it
mode
WDIFn
A write access to a mailbox was denied
GIL bit
Cleared by writing a 1 to it
AAIFn
A transmission request was aborted
GIL bit
Cleared by clearing the set AAn bit.
GMIFn
One of the mailboxes successfully
MILn bit
Cleared by appropriate handling of
transmitted/received a message
the interrupt causing condition. Cleared by
writing a 1 to the ap-propriate bit in CANTA
or CANRMP registers
TCOFn
The MSB of the the TSC has changed from GIL bit
Cleared by writing a 1 to it
0 to 1
MTOFn
One of the mailboxes did not
MILn bit
Cleared by clearing the set TOSn
transmit/receive within the specified time
bit.
frame.
(1)
Key to interpreting the table above:
1) Interrupt flag: This is the name of the interrupt flag bit as applicable to CANGIF0/CANGIF1 registers.
2) Interrupt condition: This column illustrates the conditions that cause the interrupt to be asserted.
3) GIF0/GIF1 determination: Interrupt flag bits can be set in either CANGIF0 or CANGIF1 registers. This is determined by either
the GIL bit in CANGIM register or MILn bit in the CANMIL register, depending on the interrupt under consideration. This column
illustrates whether a particular interrupt is dependant on GIL bit or MILn bit.
4) Clearing mechanism: This column explains how a flag bit can be cleared. Some bits are cleared by writing a 1 to it. Other bits
are cleared by manipulating some other bit in the CAN control register.
To configure for interrupt handling, the mailbox interrupt level register (CANMIL), the mailbox interrupt
mask register (CANMIM), and the global interrupt mask register (CANGIM) need to be configured. The
steps to do this are described below:
1. Write the CANMIL register. This defines whether a successful transmission asserts interrupt line 0 or 1.
For example, CANMIL = 0xFFFFFFFF sets all mailbox interrupts to level 1.
2. Configure the mailbox interrupt mask register (CANMIM) to mask out the mailboxes that should not
cause an interrupt. This register could be set to 0xFFFFFFFF, which enables all mailbox interrupts.
Mailboxes that are not used do not cause any interrupts anyhow.
3. Now configure the CANGIM register. The flags AAIM, WDIM, WUIM, BOIM, EPIM, and WLIM
(GIM.14-9) should always be set (enabling these interrupts). In addition, the GIL (GIM.2) bit can be set
to have the global interrupts on another level than the mailbox interrupts. Both the I1EN (GIM.1) and
I0EN (GIM.0) flags should be set to enable both interrupt lines. The flag RMLIM (GIM.11) can also be
set depending on the load of the CPU.
78
eCAN Configuration
SPRU074F – May 2002 – Revised January 2009
