Interrupt Registers
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Figure 2-16. Global Interrupt Flag 0 Register (CANGIF0)
31
24
Reserved
R-x
23
18
17
16
Reserved
MTOF0
TCOF0
R-x
R-0
RC-0
15
14
13
12
11
10
9
8
GMIF0
AAIF0
WDIF0
WUIF0
RMLIF0
BOIF0
EPIF0
WLIF0
R/W-0
R-0
RC-0
RC-0
R-0
RC-0
RC-0
RC-0
7
5
4
3
2
1
0
Reserved
MIV0.4
MIV0.3
MIV0.2
MIV0.1
MIV0.0
R/W-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read; C = Clear; -
n
= value after reset
Figure 2-17. Global Interrupt Flag 1 Register (CANGIF1)
31
24
Reserved
R-x
23
18
17
16
Reserved
MTOF1
TCOF1
R-x
R-0
RC-0
15
14
13
12
11
10
9
8
GMIF1
AAIF1
WDIF1
WUIF1
RMLIF1
BOIF1
EPIF1
WLIF1
R/W-0
R-0
RC-0
RC-0
R-0
RC-0
RC-0
RC-0
7
5
4
3
2
1
0
Reserved
MIV0.4
MIV0.3
MIV0.2
MIV0.1
MIV0.0
R/W-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read; C = Clear; -
n
= value after reset
Note: eCAN only, reserved in the SCC
Note:
The following bit descriptions are applicable to both the CANGIF0 and CANGIF1 registers.
For the following interrupt flags, whether they are set in the CANGIF0 or the CANGIF1
register is determined by the value of the GIL bit in the CANGIM register: TCOF
n
, AAIF
n
,
WDIF
n
, WUIF
n
, RMLIF
n
, BOIF
n
, EPIF
n
, and WLIF
n
.
If GIL = 0, these flags are set in the CANGIF0 register; if GIL = 1, they are set in the
CANGIF1 register.
Similarly, the choice of the CANGIF0 and CANGIF1 register for the MTOFn and GMIFn bits
is determined by the MILn bit in the CANMIL register.
46
eCAN Registers
SPRU074F – May 2002 – Revised January 2009