1.3.2 Memory Map
1.3.2.1
32-bit Access to Control and Status Registers
www.ti.com
eCAN Controller Overview
The eCAN module has two different address segments mapped in the memory. The first segment is used
to access the control registers, the status registers, the acceptance masks, the time stamp, and the
time-out of the message objects. The access to the control and status registers is limited to 32-bit wide
accesses. The local acceptance masks, the time stamp registers, and the time-out registers can be
accessed 8-bit, 16-bit and 32-bit wide. The second address segment is used to access the mailboxes.
This memory range can be accessed 8-bit, 16-bit and 32-bit wide. Each of these two memory blocks,
shown in
, uses 512 bytes of address space.
The message storage is implemented by a RAM that can be addressed by the CAN controller or the CPU.
The CPU controls the CAN controller by modifying the various mailboxes in the RAM or the additional
registers. The contents of the various storage elements are used to perform the functions of the
acceptance filtering, message transmission, and interrupt handling.
The mailbox module in the eCAN provides 32 message mailboxes of 8-byte data length, a 29-bit identifier,
and several control bits. Each mailbox can be configured as either transmit or receive. In the eCAN mode,
each mailbox has its individual acceptance mask.
Note:
LAMn, MOTSn and MOTOn registers and mailboxes not used in an application (disabled in
the CANME register) may be used as general-purpose data memory by the CPU.
As indicated in
, only 32-bit accesses are allowed to the Control and Status registers. 16-bit
access to these registers could potentially corrupt the register contents or return false data. The DSP
header files released by TI employs a shadow register structure that aids in 32-bit access. Following are a
few examples of how the shadow register structure may be employed to perform 32-bit reads/writes:
Example 1-1. Modifying a bit in a register
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
// Step 1
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
// Step 2
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
// Step 3
Step 1: Perform a 32-bit read to copy the entire register to its shadow
Step 2: Modify the needed bit(s) in the shadow
Step 3: Perform a 32-bit write to copy the modified shadow to the original register.
Note:
Some bits like TAn and RMPn are cleared by writing a 1 to it. Care should be taken not to
clear bits inadvertently.
Example 1-2. Checking the value of a bit in a register
do
{
ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
}while(ECanaShadow.CANTA.bit.TA25 == 0);
// Wait for TA5 bit to be set..
In the above example, the value of TA25 bit needs to be checked. This is done by first copying the entire
CANTA register to its shadow (using a 32-bit read) and then checking the relevant bit, repeating this
operation until that condition is satisfied. TA25 bit should NOT be checked with the following statement:
while(ECanaRegs.CANTA.bit.TA25 == 0);
SPRU074F – May 2002 – Revised January 2009
Architecture
15