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2.15 Interrupt Registers
2.15.1 Global Interrupt Flag Registers (CANGIF0/CANGIF1)
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Interrupt Registers
Interrupts are controlled by the interrupt flag registers, interrupt mask registers and mailbox interrupt level
registers. These registers are described in the following subsections.
These registers allow the CPU to identify the interrupt source.
The interrupt flag bits are set if the corresponding interrupt condition did occur. The global interrupt flags
are set depending on the setting of the GIL bit in the CANGIM register. If that bit is set, the global
interrupts set the bits in the CANGIF1 register; otherwise, in the CANGIF0 register. This also applies to
the Interrupt Flags AAIF and RMLIF. These bits are set according to the setting of the appropriate GIL bit
in the CANGIM register.
The following bits are set regardless of the corresponding interrupt mask bits in the CANGIM register:
MTOF
n
, WDIF
n
, BOIF
n
, TCOF
n
, WUIF
n
, EPIF
n
, AAIF
n
, RMLIF
n
, and WLIF
n
.
For any mailbox, the GMIFn bit is set only when the corresponding mailbox interrupt mask bit (in the
CANMIM register) is set.
If all interrupt flags are cleared and a new interrupt flag is set the interrupt output line is activated when the
corresponding interrupt mask bit is set. The interrupt line stays active until the interrupt flag is cleared by
the CPU by writing a 1 to the appropriate bit or by clearing the interrupt-causing condition.
The GMIFx flags must be cleared by writing a 1 to the appropriate bit in the CANTA register or the
CANRMP register (depending on mailbox configuration) and cannot be cleared in the CANGIFx register.
After clearing one or more interrupt flags and one or more interrupt flags still set, a new interrupt is
generated. The interrupt flags are cleared by writing a 1 to the corresponding bit location. If the GMIFx is
set the Mailbox Interrupt Vector MIVx indicates the mailbox number of the mailbox that caused the setting
of the GMIFx. In case more than one mailbox interrupt is pending, it always displays the highest mailbox
interrupt vector assigned to that interrupt line.
SPRU074F – May 2002 – Revised January 2009
eCAN Registers
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