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2.15.2 Global Interrupt Mask Register (CANGIM)
Interrupt Registers
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The set up for the interrupt mask register is the same as for the interrupt flag register. If a bit is set, the
corresponding interrupt is enabled. This register is EALLOW protected.
Figure 2-18. Global Interrupt Mask Register (CANGIM)
31
18
17
16
Reserved
MTOM
TCOM
R-0
R/WP-
R/WP-
0
0
15
14
13
12
11
10
9
8
Reserved
AAIM
WDIM
WUIM
RMLIM
BOIM
EPIM
WLIM
R-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
3
2
1
0
Reserved
GIL
I1EN
I0EN
R-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R = Read; W = Write; WP = Write in EALLOW mode only; -
n
= value after reset
Table 2-15. Global Interrupt Mask Register (CANGIM) Field Descriptions
Bit
Field
Value
Description
31:18
Reserved
Reads are undefined and writes have no effect.
17
MTOM
Mailbox time-out interrupt mask
1
Enabled
0
Disabled
16
TCOM
Time stamp counter overflow mask
1
Enabled
0
Disabled
15
Reserved
Reads are undefined and writes have no effect.
14
AAIM
Abort Acknowledge Interrupt Mask.
1
Enabled
0
Disabled
13
WDIM
Write denied interrupt mask
1
Enabled
0
Disabled
12
WUIM
Wake-up interrupt mask
1
Enabled
0
Disabled
11
RMLIM
Received-message-lost interrupt mask
1
Enabled
0
Disabled
10
BOIM
Bus-off interrupt mask
1
Enabled
0
Disabled
9
EPIM
Error-passive interrupt mask
1
Enabled
0
Disabled
48
eCAN Registers
SPRU074F – May 2002 – Revised January 2009