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Texas Instruments TMS320x281 series, Reference Manual

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3.4.3.2

Handling Mailbox Interrupts

3.4.3.3

Interrupt Handling Sequence

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Interrupts

This configuration puts all mailbox interrupts on line 1 and all system interrupts on line 0. Thus, the CPU
can handle all system interrupts (which are always serious) with high priority, and the mailbox interrupts
(on the other line) with a lower priority. All messages with a high priority can also be directed to the
interrupt line 0.

There are three interrupt flags for mailbox interrupts. These are listed below:

GMIF0/GMIF1: One of the objects has received or transmitted a message. The number of the mailbox is
in MIV0/MIV1(GIF0.4-0/GIF1.4-0). The normal handling routine is as follows:

1. Do a half-word read on the GIF register that caused the interrupt. If the value is negative, a mailbox

caused the interrupt. Otherwise, check the AAIF0/AAIF1 (GIF0.14/GIF1.14) bit (abort-acknowledge
interrupt flag) or the RMLIF0/RMLIF1 (GIF0.11/GIF1.11) bit (receive-message-lost interrupt flag).
Otherwise, a system interrupt has occurred. In this case, each of the system-interrupt flags must be
checked.

2. If the RMLIF (GIF0.11) flag caused the interrupt, the message in one of the mailboxes has been

overwritten by a new one. This should not happen in normal operation. The CPU needs to clear that
flag by writing a 1 to it. The CPU must check the receive-message-lost register (RML) to find out which
mailbox caused that interrupt. Depending on the application, the CPU has to decide what to do next.
This interrupt comes together with an GMIF0/GMIF1 interrupt.

3. If the AAIF (GIF.14) flag caused the interrupt, a send transmission operation was aborted by the CPU.

The CPU should check the abort acknowledge register (AA.31-0) to find out which mailbox caused the
interrupt and send that message again if requested. The flag must be cleared by writing a 1 to it.

4. If the GMIF0/GMIF1 (GIF0.15/GIF1.15) flag caused the interrupt, the mailbox number that caused the

interrupt can be read from the MIV0/MIV1 (GIF0.4-0/GIF1.4-0) field. This vector can be used to jump to
a location where that mailbox is handled. If it is a receive mailbox, the CPU should read the data as
described above and clear the RMP.31-0 flag by writing a 1 to it. If it is a send mailbox, no further
action is required, unless the CPU needs to send more data. In this case, the normal send procedure
as described above is necessary. The CPU needs to clear the transmit acknowledge bit (TA.31-0) by
writing a 1 to it.

In order for the CPU core to recognize and service CAN interrupts, the following must be done in any CAN
ISR:

1. The flag bit in the CANGIF0/CANGIF1 register which caused the interrupt in the first place must be

cleared. There are two kinds of bits in these registers:

a. the very same bit that needs to be cleared. The following bits fall under this category: TCOFn,

WDIFn, WUIFn, BOIFn, EPIFn, WLIFn

b. The second group of bits are cleared by writing to the corresponding bits in the associated

registers. The following bits fall under this category: MTOFn, GMIFn, AAIFn, RMLIFn

i.

The MTOFn bit is cleared by clearing the corresponding bit in the TOS register. For example, if
mailbox 27 caused a time-out condition due to which the MTOFn bit was set, the ISR (after
taking appropriate actions for the timeout condition) needs to clear the TOS27 bit in order to
clear the MTOFn bit.

ii.

The GMIFn bit is cleared by clearing the appropriate bit in TA or RMP register. For example, if
mailbox 19 has been configured as a transmit mailbox and has completed a transmission,
TA19 is set, which in turn sets GMIFn. The ISR (after taking appropriate actions) needs to clear
the TA19 bit in order to clear the GMIFn bit. If mailbox 8 has been configured as a receive
mailbox and has completed a reception, RMP8 is set, which in turn sets GMIFn. The ISR (after
taking appropriate actions) needs to clear the RMP8 bit in order to clear the GMIFn bit.

iii. The AAIFn bit is cleared by clearing the corresponding bit in the AA register. For example, if

mailbox 13’s transmission was aborted due to which the AAIFn bit was set, the ISR needs to
clear the AA13 bit in order to clear the AAIFn bit.

iv. The RMLIFn bit is cleared by clearing the corresponding bit in the RMP register. For example, if

mailbox 13’s message was overwritten due to which the RMLIFn bit was set, the ISR needs to
clear the RMP13 bit in order to clear the RMLIFn bit.

SPRU074F – May 2002 – Revised January 2009

eCAN Configuration

79

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Summary of Contents for TMS320x281 series

Page 1: ...TMS320x281x Enhanced Controller Area Network eCAN Reference Guide Literature Number SPRU074F May 2002 Revised January 2009 ...

Page 2: ...2 SPRU074F May 2002 Revised January 2009 Submit Documentation Feedback ...

Page 3: ...knowledge Register CANTA 30 2 6 Abort Acknowledge Register CANAA 31 2 7 Received Message Pending Register CANRMP 32 2 8 Received Message Lost Register CANRML 33 2 9 Remote Frame Pending Register CANRFP 34 2 9 1 Handling of Remote Frames 34 2 10 Global Acceptance Mask Register CANGAM 36 2 11 Master Control Register CANMC 37 2 11 1 CAN Module Action in SUSPEND 39 2 12 Bit Timing Configuration Regist...

Page 4: ...EALLOW Protection 72 3 2 Steps to Configure eCAN 72 3 2 1 Configuring a Mailbox for Transmit 73 3 2 2 Transmitting a Message 73 3 2 3 Configuring Mailboxes for Receive 73 3 2 4 Receiving a Message 74 3 2 5 Handling of Overload Situations 74 3 3 Handling of Remote Frame Mailboxes 74 3 3 1 Requesting Data From Another Node 74 3 3 2 Answering a Remote Request 75 3 3 3 Updating the Data Field 75 3 4 I...

Page 5: ...ag 0 Register CANGIF0 46 2 17 Global Interrupt Flag 1 Register CANGIF1 46 2 18 Global Interrupt Mask Register CANGIM 48 2 19 Mailbox Interrupt Mask Register CANMIM 50 2 20 Mailbox Interrupt Level Register CANMIL 51 2 21 Overwrite Protection Control Register CANOPC 52 2 22 TX I O Control Register CANTIOC 53 2 23 RX I O Control Register CANRIOC 54 2 24 Time Stamp Counter Register CANTSC 56 2 25 Mess...

Page 6: ...t Mask Register CANGIM Field Descriptions 48 2 16 Mailbox Interrupt Mask Register CANMIM Field Descriptions 50 2 17 Mailbox Interrupt Level Register CANMIL Field Descriptions 51 2 18 Overwrite Protection Control Register CANOPC Field Descriptions 52 2 19 TX I O Control Register CANTIOC Field Descriptions 53 2 20 RX I O Control Register CANRIOC Field Descriptions 54 2 21 Time Stamp Counter Register...

Page 7: ...is a 12 bit pipelined ADC The analog circuits of this converter referred to as the core in this document include the front end analog multiplexers MUXs sample and hold S H circuits the conversion core voltage regulators and other analog supporting circuits Digital circuits referred to as the wrapper in this document include programmable conversion sequencer result registers interface to analog cir...

Page 8: ...escribes other contents of the device on chip boot ROM and identifies where all of the information is located within that memory Tools Guides SPRU513 TMS320C28x Assembly Language Tools User s Guide describes the assembly language tools assembler and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS...

Page 9: ...Refer to theTMS320x28xx 28xxx DSP Peripheral Reference Guide SPRU566 for a list of other devices with a eCAN module of the same type to determine the differences between types and for a list of device specific differences within a type Some devices have a second CAN module eCAN B The word eCAN is generically used to refer to the CAN modules The specific module reference A or B is used where approp...

Page 10: ...gainst reception of new message Allows dynamically programmable priority of transmit message Employs a programmable interrupt scheme with two interrupt levels Employs a programmable interrupt on transmission or reception time out Low power mode Programmable wake up on bus activity Automatic reply to a remote request message Automatic retransmission of a frame in case of loss of arbitration or erro...

Page 11: ...ical to the High end CAN Controller HECC used in the TMS470 series microcontrollers from Texas Instruments with some minor changes The eCAN module features several enhancements such as increased number of mailboxes with individual acceptance masks time stamping etc over the CAN module featured in 240x series of DSPs For this reason code written for 240x CAN modules cannot be directly ported to eCA...

Page 12: ...ransmitted by any node on a bus error detection Overload frames that provide an extra delay between the preceding and the succeeding data frames or remote frames In addition CAN specification version 2 0B defines two different formats that differ in the length of the identifier field standard frames with an 11 bit identifier and extended frames with 29 bit identifier CAN standard data frames conta...

Page 13: ...smit to the CPK according to the message s priority The eCAN is a CAN controller with an internal 32 bit architecture The eCAN module consists of The CAN protocol kernel CPK The message controller comprising The memory management unit MMU including the CPU interface and the receive control unit acceptance filtering and the timer management unit Mailbox RAM enabling the storage of 32 messages Contr...

Page 14: ...d period of time time out The time stamping feature is available in eCAN mode only To initiate a data transfer the transmission request bit TRS n has to be set in the corresponding control register The entire transmission procedure and possible error handling are then performed without any CPU involvement If a mailbox has been configured to receive messages the CPU easily reads its data registers ...

Page 15: ...t used in an application disabled in the CANME register may be used as general purpose data memory by the CPU As indicated in Section 1 3 2 only 32 bit accesses are allowed to the Control and Status registers 16 bit access to these registers could potentially corrupt the register contents or return false data The DSP header files released by TI employs a shadow register structure that aids in 32 b...

Page 16: ...rol CANTOC Time Out Status CANTOS Reserved eCAN A Control and Status Registers Message Identifier MSGID 32 bits 61E8h 61E9h Message Control MSGCTRL 32 bits Message Data Low CANMDL 4 bytes Message Data High CANMDH 4 bytes Message Mailbox 16 Bytes Control and Status Registers 6000h 603Fh Local Acceptance Masks LAM 32 32 Bit RAM 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN A Registers 512 Bytes Message O...

Page 17: ...GIF1 Time Out Control CANTOC Time Out Status CANTOS Reserved eCAN B Control and Status Registers Message Identifier MSGID 63E8h 63E9h Message Control MSGCTRL Message Data Low CANMDL Message Data High CANMDH Message Mailbox 16 Bytes Control and Status Registers 6200h 623Fh Local Acceptance Masks LAM 32 32 Bit RAM 6240h 627Fh 6280h 62BFh 62C0h 62FFh eCAN B Memory 512 Bytes Message Object Time Stamps...

Page 18: ... configuration CANES 0x6018 0x6218 1 Error and status CANTEC 0x601A 0x621A 1 Transmit error counter CANREC 0x601C 0x621C 1 Receive error counter CANGIF0 0x601E 0x621E 1 Global interrupt flag 0 CANGIM 0x6020 0x6220 1 Global interrupt mask CANGIF1 0x6022 0x6222 1 Global interrupt flag 1 CANMIM 0x6024 0x6224 1 Mailbox interrupt mask CANMIL 0x6026 0x6226 1 Mailbox interrupt level CANOPC 0x6028 0x6228 ...

Page 19: ... area of the message mailboxes that are not used for storing messages as normal memory Each mailbox contains The message identifier 29 bits for extended identifier 11 bits for standard identifier The identifier extension bit IDE MSGID 31 The acceptance mask enable bit AME MSGID 30 The auto answer mode bit AAM MSGID 29 The transmit priority level TPL MSGCTRL 12 8 The remote transmission request bit...

Page 20: ...8 6169h 616A 616Bh 616C 616Dh 616E 616Fh 14 6170 6171h 6172 6173h 6174 6175h 6176 6177h 15 6178 6179h 617A 617Bh 617C 617Dh 617E 617Fh 16 6180 6181h 6182 6183h 6184 6185h 6186 6187h 17 6188 6189h 618A 618Bh 618C 618Dh 618E 618Fh 18 6190 6191h 6192 6193h 6194 6195h 6196 6197h 19 6198 6199h 619A 619Bh 619C 619Dh 619E 619Fh 20 61A0 61A1h 61A2 61A3h 61A4 61A5h 61A6 61A7h 21 61A8 61A9h 61AA 61ABh 61AC ...

Page 21: ...605Ah 605Bh 609Ah 609Bh 60DAh 60DBh 14 605Ch 605Dh 609Ch 609Dh 60DCh 60DDh 15 605Eh 605Fh 609Eh 609Fh 60DEh 60DFh 16 6060h 6061h 60A0h 60A1h 60E0h 60E1h 17 6062h 6063h 60A2h 60A3h 60E2h 60E3h 18 6064h 6065h 60A4h 60A5h 60E4h 60E5h 19 6066h 6067h 60A6h 60A7h 60E6h 60E7h 20 6068h 6069h 60A8h 60A9h 60E8h 60E9h 21 606Ah 606Bh 60AAh 60ABh 60EAh 60EBh 22 606Ch 606Dh 60ACh 60ADh 60ECh 60EDh 23 606Eh 606F...

Page 22: ...369h 636A 636Bh 636C 636Dh 636E 636Fh 14 6370 6371h 6372 6373h 6374 6375h 6376 6377h 15 6378 6379h 637A 637Bh 637C 637Dh 637E 637Fh 16 6380 6381h 6382 6383h 6384 6385h 6386 6387h 17 6388 6389h 638A 638Bh 638C 638Dh 638E 638Fh 18 6390 6391h 6392 6393h 6394 6395h 6396 6397h 19 6398 6399h 639A 639Bh 639C 639Dh 639E 639Fh 20 63A0 63A1h 63A2 63A3h 63A4 63A5h 63A6 63A7h 21 63A8 63A9h 63AA 63ABh 63AC 63A...

Page 23: ...20 6268h 6269h 62A8h 62A9h 62E8h 62E9h 21 626Ah 626Bh 62AAh 62ABh 62EAh 62EBh 22 626Ch 626Dh 62ACh 62ADh 62ECh 62EDh 23 626Eh 626Fh 62AEh 62AFh 62EEh 62EFh 24 6270h 6271h 62B0h 62B1h 62F0h 62F1h 25 6272h 6273h 62B2h 62B3h 62F2h 62F3h 26 6274h 6275h 62B4h 62B5h 62F4h 62F5h 27 6276h 6277h 62B6h 62B7h 62F6h 62F7h 28 6278h 6279h 62B8h 62B9h 62F8h 62F9h 29 627Ah 627Bh 62BAh 62BBh 62FAh 62FBh 30 627Ch 6...

Page 24: ... RMP n RMP 31 0 has to be reset by the CPU after reading the data If a second message has been received for this mailbox and the receive message pending bit is already set the corresponding message lost bit RML n RML 31 0 is set In this case the stored message is overwritten with the new data if the overwrite protection bit OPC n OPC 31 0 is cleared otherwise the next mailboxes are checked If a ma...

Page 25: ...gister CANRMP 32 2 8 Received Message Lost Register CANRML 33 2 9 Remote Frame Pending Register CANRFP 34 2 10 Global Acceptance Mask Register CANGAM 36 2 11 Master Control Register CANMC 37 2 12 Bit Timing Configuration Register CANBTC 40 2 13 Error and Status Register CANES 42 2 14 CAN Error Counter Registers CANTEC CANREC 44 2 15 Interrupt Registers 45 2 16 Overwrite Protection Control Register...

Page 26: ...ble bits After power up all bits in CANME are cleared Disabled mailboxes can be used as additional memory for the CPU 1 The corresponding mailbox is enabled for the CAN module The mailbox must be disabled before writing to the contents of any identifier field If the corresponding bit in CANME is set the write access to the identifier of a mailbox is denied 0 The corresponding mailbox RAM area is d...

Page 27: ...W 0 LEGEND R W Read Write n value after reset Table 2 2 Mailbox Direction Register CANMD Field Descriptions Bit Field Value Description 31 0 CANMD 31 0 Mailbox direction bits After power up all bits are cleared 1 The corresponding mailbox is configured as a receive mailbox 0 The corresponding mailbox is configured as a transmit mailbox SPRU074F May 2002 Revised January 2009 eCAN Registers 27 Submi...

Page 28: ...ox can be used to request a data frame from another mode If the CPU tries to set a bit while the eCAN module tries to clear it the bit is set Setting CANTRS n causes the particular message n to be transmitted Several bits can be set simultaneously Therefore all messages with the TRS bit set are transmitted in turn starting with the mailbox having the highest mailbox number highest priority unless ...

Page 29: ...l operation or when an aborted transmission due to a lost arbitration or an error condition is detected on the CAN bus line When a transmission is aborted the corresponding status bit AA 31 0 is set When a transmission is successful the status bit TA 31 0 is set The status of the transmission request reset can be read from the TRS 31 0 bit The bits in CANTRR are set by writing a 1 from the CPU Fig...

Page 30: ... interrupt has been generated Writing a 0 has no effect If the CPU tries to reset the bit while the CAN tries to set it the bit is set After power up all bits are cleared Figure 2 5 Transmission Acknowledge Register CANTA 31 0 TA 31 0 RC 0 LEGEND RC Read Clear n value after reset Table 2 5 Transmission Acknowledge Register CANTA Field Descriptions Bit Field Value Description 31 0 TA 31 0 Transmit ...

Page 31: ...it and the CAN tries to set the bit at the same time the bit is set After power up all bits are cleared Figure 2 6 Abort Acknowledge Register CANAA 31 0 AA 31 0 RC 0 LEGEND RC Read Clear n value after reset Table 2 6 Abort Acknowledge Register CANAA Field Descriptions Bit Field Value Description 31 0 AA 31 0 Abort acknowledge bits 1 If the transmission of the message in mailbox n is aborted the bi...

Page 32: ...he corresponding bit location If the CPU tries to reset a bit and the CAN tries to set the bit at the same time the bit is set The bits in the CANRMP register can set GMIF0 GMIF1 GIF0 15 GIF1 15 if the corresponding interrupt mask bit in the CANMIM register is set The GMIF0 GMIF1 bit initiates an interrupt Figure 2 7 Received Message Pending Register CANRMP 31 0 RMP 31 0 RC 0 LEGEND RC Read Clear ...

Page 33: ...changed if the OPC n OPC 31 0 bit is set If one or more of the bits in the CANRML register are set the RMLIF GIF0 11 GIF1 11 bit is also set This can initiate an interrupt if the RMLIM GIM 11 bit is set Figure 2 8 Received Message Lost Register CANRML 31 0 RML 31 0 R 0 LEGEND R Read n value after reset Table 2 8 Received Message Lost Register CANRML Field Descriptions Bit Field Value Description 3...

Page 34: ...rder In the case of a matching identifier with the message object configured as send mailbox and AAM MSGID 29 in this message object set this message object is marked as to be sent TRS n is set In case of a matching identifier with the mailbox configured as a send mailbox and bit AAM in this mailbox is not set this message is not received in that mailbox After finding a matching identifier in a se...

Page 35: ...quest message object is able to transmit a remote request frame and to wait for the corresponding data frame 4 A reply message object is able to transmit a data frame whenever a remote request frame is received for the corresponding identifier Note When a remote transmission request is successfully transmitted with a message object configured in request mode the CANTA register is not set and no in...

Page 36: ...mask register are used for the filter In case of a standard frame only the first eleven bits bit 28 to 18 of the identifier and the global acceptance mask are used The IDE bit of the receive mailbox is a don t care and is overwritten by the IDE bit of the transmitted message The filtering criterion must be satisfied in order to receive a message The number of bits to be compared is a function of t...

Page 37: ...er clear bit This bit is reserved in SCC mode and it is EALLOW protected 1 The time stamp counter is reset to 0 after a successful transmission or reception of mailbox 16 0 The time stamp counter is not reset 14 TCC Time stamp counter MSB clear bit This bit is reserved in SCC mode and it is EALLOW protected 1 The MSB of the time stamp counter is reset to 0 The TCC bit is reset after one clock cycl...

Page 38: ... mailbox using the CDR bit the CAN module fails to transmit the new data and transmits the old data instead To avoid this reset transmission in that mailbox using the TRRn bit and set the TRSn bit again The new data is then transmitted 0 The CPU requests normal operation 7 ABO Auto bus on This bit is EALLOW protected 1 After the bus off state the module goes back automatically into bus on state af...

Page 39: ...e The TEC is modified after transmission of the frame accordingly 4 If the node was receiving when SUSPEND is requested it goes to SUSPEND state after transmitting the acknowledgment bit If there is any error the node sends an error frame and go to SUSPEND state The REC is modified accordingly before going to SUSPEND state 5 If there is no traffic on the CAN bus and SUSPEND removal is requested th...

Page 40: ...by where SYSCLKOUT is the frequency of the CAN module clock Note that the CAN module is clocked at the same frequency as the CPU at SYSCLKOUT BRPreg denotes the register value of the prescaler i e value written into bits 23 16 of the CANBTC register This value is automatically enhanced by 1 when the CAN module accesses it The enhanced value is denoted by the symbol BRP BRP BRPreg 1 BRP is programm...

Page 41: ... the TSEG1 segment in TQ units TSEG1 combines PROP_SEG and PHASE_SEG1 segments TSEG1 PROP_SEG PHASE_SEG1 where PROP_SEG and PHASE_SEG1 are the length of these two segments in TQ units TSEG1reg denotes the register value of time segment 1 i e the value written into bits 6 3 of the CANBTC register This value is automatically enhanced by 1 when the CAN module accesses it This enhanced value is denote...

Page 42: ...rm error detected the CAN module was able to send and receive correctly 23 BE Bit error flag 1 The received bit does not match the transmitted bit outside of the arbitration field or during transmission of the arbitration field a dominant bit was sent but a recessive bit was received 0 No bit error detected 22 SA1 Stuck at dominant error The SA1 bit is always at 1 after a hardware reset a software...

Page 43: ...ed suspend mode 0 The module is not in suspend mode 4 CCE Change configuration enable This bit displays the configuration access right This bit is set after a latency of one clock cycle 1 The CPU has write access to the configuration registers 0 The CPU is denied write access to the configuration registers Note The reset state of the CCE bit is 1 That is upon reset you can write to the bit timing ...

Page 44: ...he receive error counter will not be increased anymore When a message was received correctly the counter is set again to a value between 119 and 127 compare with CAN specification After reaching the bus off state the transmit error counter is undefined while the receive error counter changes its function After reaching the bus off state the receive error counter is cleared It is then incremented a...

Page 45: ...the GMIFn bit is set only when the corresponding mailbox interrupt mask bit in the CANMIM register is set If all interrupt flags are cleared and a new interrupt flag is set the interrupt output line is activated when the corresponding interrupt mask bit is set The interrupt line stays active until the interrupt flag is cleared by the CPU by writing a 1 to the appropriate bit or by clearing the int...

Page 46: ...0 RC 0 RC 0 7 5 4 3 2 1 0 Reserved MIV0 4 MIV0 3 MIV0 2 MIV0 1 MIV0 0 R W 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read C Clear n value after reset Note eCAN only reserved in the SCC Note The following bit descriptions are applicable to both the CANGIF0 and CANGIF1 registers For the following interrupt flags whether they are set in the CANGIF0 or the CANGIF1 register is determined by the valu...

Page 47: ...ation when the MBX is still enabled the WDIF bit will be set and a CAN interrupt asserted 0 The CPU write access to the mailbox was successful 12 WUIF0 WUIF1 Wake up interrupt flag 1 During local power down this flag indicates that the module has left sleep mode 0 The module is still in sleep mode or normal operation 11 RMLIF0 1 Receive message lost interrupt flag 1 At least for one of the receive...

Page 48: ...alue after reset Table 2 15 Global Interrupt Mask Register CANGIM Field Descriptions Bit Field Value Description 31 18 Reserved Reads are undefined and writes have no effect 17 MTOM Mailbox time out interrupt mask 1 Enabled 0 Disabled 16 TCOM Time stamp counter overflow mask 1 Enabled 0 Disabled 15 Reserved Reads are undefined and writes have no effect 14 AAIM Abort Acknowledge Interrupt Mask 1 En...

Page 49: ...ne 0 All global interrupts are mapped to the ECAN0INT interrupt line 1 I1EN Interrupt 1 enable 1 This bit globally enables all interrupts for the ECAN1INT line if the corresponding masks are set 0 The ECAN1INT interrupt line is disabled 0 I0EN Interrupt 0 enable 1 This bit globally enables all interrupts for the ECAN0INT line if the corresponding masks are set 0 The ECAN0INT interrupt line is disa...

Page 50: ...terrupt Mask Register CANMIM Field Descriptions Bit Field Value Description 31 0 MIM 31 0 Mailbox interrupt mask After power up all interrupt mask bits are cleared and the interrupts are disabled These bits allow any mailbox interrupt to be masked individually 1 Mailbox interrupt is enabled An interrupt is generated if a message has been transmitted successfully in case of a transmit mailbox or if...

Page 51: ... 2 20 Mailbox Interrupt Level Register CANMIL 31 0 MIL 31 0 R W 0 LEGEND R W Read Write n value after reset Table 2 17 Mailbox Interrupt Level Register CANMIL Field Descriptions Bit Field Value Description 31 0 MIL 31 0 Mailbox interrupt level These bits allow any mailbox interrupt level to be selected individually 1 The mailbox interrupt is generated on interrupt line 1 0 The mailbox interrupt is...

Page 52: ...t OPC n is cleared to 0 the old message is overwritten by the new one This is notified by setting the receive message lost bit RML n For read write operations only 32 bit access is supported Figure 2 21 Overwrite Protection Control Register CANOPC 31 0 OPC 31 0 R W 0 LEGEND R W Read Write n value after reset Table 2 18 Overwrite Protection Control Register CANOPC Field Descriptions Bit Field Value...

Page 53: ...ed TXFU Reserved NC R 0 RWP 0 LEGEND RWP Read in all modes write in EALLOW mode only R Read only n value after reset Table 2 19 TX I O Control Register CANTIOC Field Descriptions Bit Field Value Description 31 4 Reserved Reads are undefined and writes have no effect 3 TXFUNC This bit must be set for CAN module function 1 The CANTX pin is used for the CAN transmit functions 0 Reserved 2 0 Reserved ...

Page 54: ...Read only n value after reset x indeterminate Table 2 20 RX I O Control Register CANRIOC Field Descriptions Bit Field Value Description 31 4 Reserved Reads are undefined and writes have no effect 3 RXFUNC This bit must be set for CAN module function 1 The CANRX pin is used for the CAN receive functions 0 Reserved 2 0 Reserved Reserved eCAN Registers 54 SPRU074F May 2002 Revised January 2009 Submit...

Page 55: ...s been transmitted The counter is driven from the bit clock of the CAN bus line The timer is stopped during the initialization mode or if the module is in sleep or suspend mode After power up reset the free running counter is cleared The most significant bit of the TSC register is cleared by writing a 1 to TCC CANMC 14 The TSC register can also be cleared when mailbox 16 transmitted or received de...

Page 56: ...ry 1 µs Figure 2 24 Time Stamp Counter Register CANTSC 31 0 TSC31 0 R WP 0 LEGEND R Read WP Write in EALLOW enabled mode only n value after reset Note eCAN mode only reserved in the SCC Table 2 21 Time Stamp Counter Register CANTSC Field Descriptions Bit Field Value Description 31 0 TSC31 0 Time stamp counter register Value of the local network time counter used for the time stamp and the time out...

Page 57: ...25 Message Object Time Stamp Registers MOTS 31 0 MOTS31 0 R W x LEGEND R W Read Write n value after reset x indeterminate Table 2 22 Message Object Time Stamp Registers MOTS Field Descriptions Bit Field Value Description 31 0 MOTS31 0 Message object time stamp register Value of the time stamp counter TSC when the message has been actually received or transmitted SPRU074F May 2002 Revised January 2...

Page 58: ...MOTO are implemented as a RAM The state machine scans all the MOTO registers and compares them to the TSC counter value If the value in the TSC register is equal to or greater than the value in the time out register and the corresponding TRS bit applies to transmit mailboxes only is set and the TOC n bit is set the appropriate bit TOS n is set Since all the time out registers are scanned sequentia...

Page 59: ...e 2 24 Time Out Control Register CANTOC Field Descriptions Bit Field Value Description 31 0 TOC31 0 Time out control register 1 The TOC n bit must be set by the CPU to enable the time out function for mailbox n Before setting the TOC n bit the corresponding MOTO register should be loaded with the time out value relative to TSC 0 The time out function is disabled The TOS n flag is never set SPRU074...

Page 60: ...n transmission reception by the mailbox which asserted this flag in the first place It can also be cleared by the user via the CPU On a time out condition the MTOF0 1 bit and the TOS n bit is set On an eventual successful communication these bits are automatically cleared by the CPK Following are the possible behaviors usage for the MTOF0 1 bit 1 Time out condition occurs Both MTOF0 1 bit and TOS ...

Page 61: ...of the receive mailbox determines the number of bits to be compared 2 Filtering is not applicable The MSGIDs must match bit for bit in order to receive a message When AMI 1 IDE 1 The RECEIVED message had an extended identifier IDE 0 The RECEIVED message had a standard identifier When AMI 0 IDE 1 The message TO BE RECEIVED must have an extended identifier IDE 0 The message TO BE RECEIVED must have ...

Page 62: ... change while the CAN module is reading it Hence a write access to the data field is disabled for a receive mailbox For send mailboxes an access is usually denied if the TRS TRS 31 0 or the TRR TRR 31 0 flag is set In these cases an interrupt can be asserted A way to access those mailboxes is to set CDR MC 8 before accessing the mailbox data After the CPU access is finished the CPU must clear the ...

Page 63: ...riptions Bit Field Value Description 31 13 Reserved Reserved 12 8 TPL 4 0 Transmit priority level This 5 bit field defines the priority of this mailbox as compared to the other 31 mailboxes The highest number has the highest priority When two mailboxes have the same priority the one with the higher mailbox number is transmitted TPL applies only for transmit mailboxes TPL is not used in SCC mode 7 ...

Page 64: ...red for transmission CANMD n CANMD 31 0 0 or the mailbox is disabled CANME n CANME 31 0 0 If TRS n TRS 31 0 1 the registers CANMDL n and CANMDH n cannot be written unless CDR MC 8 1 with MBNR MC 4 0 set to n These settings also apply for a message object configured in reply mode AAM MSGID 29 1 Figure 2 31 Message Data Low Register With DBO 0 CANMDL 31 24 23 16 15 8 7 0 Byte 0 Byte 1 Byte 2 Byte 3 ...

Page 65: ...ANGAM and the two local acceptance mask registers of the SCC the CAN module must be set in the initialization mode see Section 3 1 Each of the 32 mailboxes of the eCAN has its own local acceptance mask LAM 0 to LAM 31 There is no global acceptance mask in the eCAN The selection of the mask to be used for the comparison depends on which mode SCC or eCAN is used The local acceptance filtering allows...

Page 66: ...er bit of an incoming message 1 Accept a 0 or a 1 don t care for the corresponding bit of the received identifier 0 Received identifier bit value must match the corresponding identifier bit of the MSGID register You can locally mask any identifier bits of the incoming message A 1 value means don t care or accept either a 0 or 1 for that bit position A 0 value means that the incoming bit value must...

Page 67: ...ation and describes the procedures to configure the eCAN module Topic Page 3 1 CAN Module Initialization 68 3 2 Steps to Configure eCAN 72 3 3 Handling of Remote Frame Mailboxes 74 3 4 Interrupts 75 3 5 CAN Power Down Mode 80 SPRU074F May 2002 Revised January 2009 eCAN Configuration 67 Submit Documentation Feedback ...

Page 68: ...egister CANGAM and the two local acceptance mask registers LAM 0 and LAM 3 the CAN module also must be set in the initialization mode The module is activated again by programming CCR CANMC 12 0 After hardware reset the initialization mode is active Note If the CANBTC register is programmed with a zero value or left with the initial value the CAN module never leaves the initialization mode i e CCE ...

Page 69: ...PHASE_SEG2 This phase is used to compensate for negative edge phase error This segment is programmable from 2 to 8 TIME QUANTA TQ and can be shortened by resynchronization In the eCAN module the length of a bit on the CAN bus is determined by the parameters TSEG1 BTC 6 3 TSEG2 BTC 2 0 and BRP BTC 23 16 TSEG1 combines the two time segments PROP_SEG and PHASE_SEG1 as defined by the CAN protocol TSEG...

Page 70: ... the network cable transceivers isolators must be taken into account before choosing the timing parameters Table 3 1 shows how the BRPreg field may be changed to achieve different bit rates with a BT of 15 for an 80 SP Table 3 1 BRP Field for Bit Rates BT 15 TSEG1reg 10 TSEG2reg 2 Sampling Point 80 CAN Bus Speed BRP CAN Module Clock 1 Mbps BRPreg 1 10 15 MHz 500 kbps BRPreg 1 20 7 5 MHz 250 kbps B...

Page 71: ...chieving Different Sampling Points With a BT of 20 TSEG1reg TSEG2reg SP 15 2 85 14 3 80 13 4 75 12 5 70 11 6 65 10 7 60 Table 3 6 shows how BRPreg field may be changed to achieve different bit rates with a BT of 20 for the sampling points shown in Table 3 5 Table 3 6 BRP Field for Bit Rates CAN Bus Speed BRP 1 Mbps BRPreg 1 5 500 kbps BRPreg 1 10 250 kbps BRPreg 1 20 125 kbps BRPreg 1 40 100 kbps ...

Page 72: ...the bit timing configuration register CANBTC If the CCE bit is set CANES 4 1 proceed to next step otherwise set the CCR bit CANMC 12 1 and wait until CCE bit is set CANES 4 1 Step 4 Program the CANBTC register with the appropriate timing values Make sure that the values TSEG1 and TSEG2 are not 0 If they are 0 the module does not leave the initialization mode Step 5 For the SCC program the acceptan...

Page 73: ... 10 is set to zero in the configuration section and MSGCTRL 1 is set to 2 the data are stored in the 2 MSBytes of CANMDL 1 b Write CANMDL 1 xxxx0000h 2 Set the corresponding flag in the transmit request register CANTRS 1 1 to start the transmission of the message The CAN module now handles the complete transmission of the CAN message 3 Wait until the transmit acknowledge flag of the corresponding ...

Page 74: ...d while the CPU was reading the old one If the CPU is not able to handle important messages fast enough it may be advisable to configure more than one mailbox for that identifier Here is an example where the objects 3 4 and 5 have the same identifier and share the same mask For the SCC the mask is LAM 3 For the eCAN each object has its own LAM LAM 3 LAM 4 and LAM 5 all of which need to be programm...

Page 75: ...data request CDR MC 8 bit and the mailbox number MBNR of that object in the master control register CANMC This tells the CAN module that the CPU wants to change the data field For example for object 1 Write MC 0x0000101 2 Write the message data into the mailbox data register For example Write CANMDL 1 xxxx0000h 3 Clear the CDR bit MC 8 to enable the object Write MC 0x00000000 There are two differe...

Page 76: ...0 1 Warning level GIL CANGIM Interrupt level select Interrupt masks Interrupt sources Interrupt level 0 flags Interrupt level 1 flags TCOIF0 TCOIF1 TCOIF TCOIM 0 1 Timer overflow RMLIF0 RMLIF1 RMLIM 0 1 CANGIM I0EN I1EN Mailbox Timeout CANMIM Interrupts www ti com Bus off interrupt the CAN module enters the bus off state Error passive interrupt the CAN module enters the error passive mode Warning ...

Page 77: ...mit event the MIM bit has to be set If a CAN message is received RMP n 1 in a receive mailbox or transmitted TA n 1 from a transmit mailbox an interrupt is asserted If a mailbox is configured as remote request mailbox CANMD n 1 MSGCTRL RTR 1 an interrupt occurs upon reception of the reply frame A remote reply mailbox generates an interrupt upon successful transmission of the reply frame CANMD n 0 ...

Page 78: ...rame 1 Key to interpreting the table above 1 Interrupt flag This is the name of the interrupt flag bit as applicable to CANGIF0 CANGIF1 registers 2 Interrupt condition This column illustrates the conditions that cause the interrupt to be asserted 3 GIF0 GIF1 determination Interrupt flag bits can be set in either CANGIF0 or CANGIF1 registers This is determined by either the GIL bit in CANGIM regist...

Page 79: ...the data as described above and clear the RMP 31 0 flag by writing a 1 to it If it is a send mailbox no further action is required unless the CPU needs to send more data In this case the normal send procedure as described above is necessary The CPU needs to clear the transmit acknowledge bit TA 31 0 by writing a 1 to it In order for the CPU core to recognize and service CAN interrupts the followin...

Page 80: ... up sequence The module waits until it detects 11 consecutive recessive bits on the CANRX pin and then it goes bus active Note The first CAN message which initiates the bus activity cannot be received This means that the first message received in power down and automatic wake up mode is lost After leaving the sleep mode the PDR and PDA bits are cleared The CAN error counters remain unchanged If th...

Page 81: ... module at all In such applications the CAN module clock can be permanently turned off resulting in some power saving This bit is not intended to put the CAN module in low power mode and should not be used for that purpose Like all other peripherals clock to the CAN module is disabled upon reset This section lists some potential failure modes in a CAN based system The failure modes listed are exte...

Page 82: ...eCAN Configuration 82 SPRU074F May 2002 Revised January 2009 Submit Documentation Feedback ...

Page 83: ...ed 2nd paragraph Figure 1 1 changed Figure Section 1 3 Added to 5th paragraph To initiate Section 1 3 2 1 Added this section Section 1 5 3 Added last sentence in 1st paragraph Section 1 5 3 Added 3rd paragraph Table 2 1 Changed field description Table 2 2 Changed field description Table 2 12 Changed bits 23 16 and 9 8 descriptions Section 2 18 1 Changed MSCC to MBCC in 3rd paragraph Table 2 26 Rem...

Page 84: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

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