![background image](http://html1.mh-extra.com/html/texas-instruments/tms320x281-series/tms320x281-series_reference-manual_1095203060.webp)
2.18.2.3 Time-Out Status Register (CANTOS)
2.18.3 Behavior/Usage of MTOF0/1 Bit in User Applications
Timer Management Unit
www.ti.com
This register holds the status information of mailboxes that have timed out.
Figure 2-28. Time-Out Status Register (CANTOS)
31
0
TOS31:0
R/C-0
LEGEND: R/C = Read/Clear; -
n
= value after reset
Table 2-25. Time-Out Status Register (CANTOS) Field Descriptions
Bit
Field
Value
Description
31:0
TOS 31:0
Time-out status register
1
Mailbox[
n
] has timed out. The value in the TSC register is larger or equal to the value in the
time-out register that corresponds to mailbox
n
and the TOC[
n
] bit is set.
0
No time-out occurred or it is disabled for that mailbox.
The TOS
n
bit is set when all three of the following conditions are met:
1. The TSC value is greater than or equal to the value in the time-out register (MOTOn).
2. The TOC
n
bit is set.
3. The TRS
n
bit is set.
The time-out registers are implemented as a RAM. The state machine scans all the time-out registers and
compares them to the time stamp counter value. Since all the time out registers are scanned sequentially,
it is possible that even though a transmit mailbox has timed out, the TOS
n
bit is not set. This can happen
when the mailbox succeeded in transmitting and clearing the TRS
n
bit before the state machine scans the
time-out register of that mailbox. This is true for the receive mailbox as well. In this case, the RMP
n
bit
can be set to 1 by the time the state machine scans the time-out register of that mailbox. However, the
receive mailbox probably did not receive the message before the time specified in the time-out register.
The MTOF0/1 bit is automatically cleared by the CPK (along with the TOS
n
bit) upon
transmission/reception by the mailbox, which asserted this flag in the first place. It can also be cleared by
the user (via the CPU). On a time-out condition, the MTOF0/1 bit (and the TOS.
n
bit) is set. On an
(eventual) successful communication, these bits are automatically cleared by the CPK. Following are the
possible behaviors/usage for the MTOF0/1 bit:
1. Time-out condition occurs. Both MTOF0/1 bit and TOS.
n
bits are set. Communication is never
successful; i.e., the frame was never transmitted (or received). An interrupt is asserted. Application
handles the issue and eventually clears both MTOF0/1 bit and TOS.
n
bit.
2. Time-out condition occurs. Both MTOF0/1 bit and TOS.
n
bits are set. However, communication is
eventually successful; i.e., the frame gets transmitted (or received). Both MTOF0/1 bit and TOS.
n
bits
are cleared automatically by the CPK. An interrupt is still asserted because, the interrupt occurrence
was recorded in the PIE module. When the ISR scans the GIF register, it doesn't see the MTOF0/1 bit
set. This is the phantom interrupt scenario. Application merely returns to the main code.
3. Time-out condition occurs. Both MTOF0/1 bit and TOS.
n
bits are set. While executing the ISR
pertaining to time-out, communication is successful. This situation must be handled carefully. The
application should not re-transmit a mailbox if the mailbox is sent between the time the interrupt is
asserted and the time the ISR is attempting to take corrective action. One way of doing this is to poll
the TM/RM bits in the GSR register. These bits indicate if the CPK is currently transmitting/receiving. If
that is the case, the application should wait till the communication is over and then check the TOS.
n
bit
again. If the communication is still not successful, then the application should take the corrective
action.
eCAN Registers
60
SPRU074F – May 2002 – Revised January 2009