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EMAC Control Module Registers
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3.9
EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT)
The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in
Figure 20
and
described in
Table 16
.
Figure 20. EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXTHRESHINTTSTAT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 16. EMAC Control Module Receive Threshold Interrupt Status Register
(CMRXTHRESHINTSTAT) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXTHRESHINTTSTAT[n]
Receive threshold interrupt status. Each bit shows the status of the corresponding
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt is not pending.
Bit n = 1, channel n receive threshold interrupt is pending.
3.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
The receive interrupt status register (CMRXINTSTAT) is shown in
Figure 21
and described in
Table 17
.
Figure 21. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXPULSEINTTSTAT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 17. EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXPULSEINTTSTAT[n]
Receive interrupt status. Each bit shows the status of the corresponding channel n receive
interrupt.
Bit n = 0, channel n receive interrupt is not pending.
Bit n = 1, channel n receive interrupt is pending.
66
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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