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46
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
.....................................
92
47
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
...............................
93
48
MAC Input Vector Register (MACINVECTOR) Field Descriptions
..................................................
94
49
MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
...................................
94
50
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
.........................
95
51
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
........................
96
52
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
.....................................
97
53
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
...............................
98
54
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
...........................
99
55
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
.........................
99
56
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
.....................................
100
57
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
...............................
100
58
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions
...............................................................................................................
101
59
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
...................................
104
60
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
......................................
105
61
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
............................................
106
62
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
.......................................
106
63
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
......
107
64
Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions
..............
107
65
Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
.....................
108
66
MAC Control Register (MACCONTROL) Field Descriptions
.......................................................
109
67
MAC Status Register (MACSTATUS) Field Descriptions
...........................................................
111
68
Emulation Control Register (EMCONTROL) Field Descriptions
...................................................
113
69
FIFO Control Register (FIFOCONTROL) Field Descriptions
.......................................................
113
70
MAC Configuration Register (MACCONFIG) Field Descriptions
..................................................
114
71
Soft Reset Register (SOFTRESET) Field Descriptions
.............................................................
114
72
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
...........................
115
73
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
............................
115
74
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
.................................................
116
75
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
.................................................
116
76
Back Off Test Register (BOFFTEST) Field Descriptions
...........................................................
117
77
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
....................................
117
78
Receive Pause Timer Register (RXPAUSE) Field Descriptions
...................................................
118
79
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
..................................................
118
80
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
..........................................
119
81
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
...........................................
120
82
MAC Index Register (MACINDEX) Field Descriptions
..............................................................
120
83
Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions
...................
121
84
Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions
...................
121
85
Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
..................................
122
86
Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
..................................
122
87
Physical Layer Definitions
..............................................................................................
132
88
Document Revision History
.............................................................................................
133
9
SPRUFI5B – March 2009 – Revised December 2010
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