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EMAC Control Module Registers

3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)

The transmit interrupt status register (CMTXINTSTAT) is shown in

Figure 22

and described in

Table 18

Figure 22. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)

Reserved

R-0

Reserved

TXPULSEINTTSTAT

R-0

LEGEND: R = Read only; -n = value after reset

Table 18. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)

Field Descriptions

Bit

Field

Value

Description

31-8

Reserved

7-0

TXPULSEINTTSTAT[n]

Transmit interrupt status. Each bit shows the status of the corresponding channel n transmit
interrupt.

Bit n = 0, channel n transmit interrupt is not pending.

Bit n = 1, channel n transmit interrupt is pending.

SPRUFI5B – March 2009 – Revised December 2010

Ethernet Media Access Controller (EMAC)/Management Data Input/Output

(MDIO)

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Summary of Contents for TMS320DM36 Series

Page 1: ...TMS320DM36x Digital Media System on Chip DMSoC Ethernet Media Access Controller EMAC User s Guide Literature Number SPRUFI5B March 2009 Revised December 2010 ...

Page 2: ...2 SPRUFI5B March 2009 Revised December 2010 Submit Documentation Feedback 2009 2010 Texas Instruments Incorporated ...

Page 3: ...3 3 EMAC Control Module Emulation Control Register CMEMCONTROL 61 3 4 EMAC Control Module Interrupt Control Register CMINTCTRL 62 3 5 EMAC Control Module Receive Threshold Interrupt Enable Register CMRXTHRESHINTEN 63 3 6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN 63 3 7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN 64 3 8 EMAC Control Module Miscellaneous In...

Page 4: ... Transmit Interrupt Mask Clear Register TXINTMASKCLEAR 93 5 11 MAC Input Vector Register MACINVECTOR 94 5 12 MAC End Of Interrupt Vector Register MACEOIVECTOR 94 5 13 Receive Interrupt Status Unmasked Register RXINTSTATRAW 95 5 14 Receive Interrupt Status Masked Register RXINTSTATMASKED 96 5 15 Receive Interrupt Mask Set Register RXINTMASKSET 97 5 16 Receive Interrupt Mask Clear Register RXINTMASK...

Page 5: ...MAC Address Low Bytes Register MACADDRLO 119 5 44 MAC Address High Bytes Register MACADDRHI 120 5 45 MAC Index Register MACINDEX 120 5 46 Transmit Channel 0 7 DMA Head Descriptor Pointer Register TXnHDP 121 5 47 Receive Channel 0 7 DMA Head Descriptor Pointer Register RXnHDP 121 5 48 Transmit Channel 0 7 Completion Pointer Register TXnCP 122 5 49 Receive Channel 0 7 Completion Pointer Register RXn...

Page 6: ...TAT 68 24 EMAC Control Module Receive Interrupts per Millisecond Register CMRXINTMAX 69 25 EMAC Control Module Transmit Interrupts per Millisecond Register CMTXINTMAX 69 26 MDIO Version Register VERSION 70 27 MDIO Control Register CONTROL 71 28 PHY Acknowledge Status Register ALIVE 72 29 PHY Link Status Register LINK 72 30 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW 73 31 MDIO L...

Page 7: ...reshold Register RXnFLOWTHRESH 107 67 Receive Channel n Free Buffer Count Register RXnFREEBUFFER 108 68 MAC Control Register MACCONTROL 109 69 MAC Status Register MACSTATUS 111 70 Emulation Control Register EMCONTROL 113 71 FIFO Control Register FIFOCONTROL 113 72 MAC Configuration Register MACCONFIG 114 73 Soft Reset Register SOFTRESET 114 74 MAC Source Address Low Bytes Register MACSRCADDRLO 115...

Page 8: ... Registers 70 23 MDIO Version Register VERSION Field Descriptions 70 24 MDIO Control Register CONTROL Field Descriptions 71 25 PHY Acknowledge Status Register ALIVE Field Descriptions 72 26 PHY Link Status Register LINK Field Descriptions 72 27 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions 73 28 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED Fie...

Page 9: ...5 Receive Channel n Free Buffer Count Register RXnFREEBUFFER Field Descriptions 108 66 MAC Control Register MACCONTROL Field Descriptions 109 67 MAC Status Register MACSTATUS Field Descriptions 111 68 Emulation Control Register EMCONTROL Field Descriptions 113 69 FIFO Control Register FIFOCONTROL Field Descriptions 113 70 MAC Configuration Register MACCONFIG Field Descriptions 114 71 Soft Reset Re...

Page 10: ...ip DMSoC The ARM subsystem is designed to give the ARM926EJ S ARM9 master control of the device In general the ARM is responsible for configuration and control of the device including the components of the ARM Subsystem the peripherals and the external memories SPRUFG8 TMS320DM36x Digital Media System on Chip DMSoC Video Processing Front End VPFE Users Guide This document describes the Video Proce...

Page 11: ...Controller Users Guide This document describes the universal serial bus USB controller in the TMS320DM36x Digital Media System on Chip DMSoC The USB controller supports data throughput rates up to 480 Mbps It provides a mechanism for data transfer between USB devices and also supports host negotiation SPRUFI0 TMS320DM36x Digital Media System on Chip DMSoC Enhanced Direct Memory Access EDMA Control...

Page 12: ...Voice Codec User s Guide This document describes the voice codec peripheral in the TMS320DM36x Digital Media System on Chip DMSoC This module can access ADC DAC data with internal FIFO Read FIFO Write FIFO The CPU communicates to the voice codec module using 32 bit wide control registers accessible via the internal peripheral bus SPRUFJ0 TMS320DM36x Digital Media System on Chip DMSoC Power Managem...

Page 13: ... as DMA master to either internal or external device memory space Hardware error handling including CRC Eight receive channels with VLAN tag discrimination for receive quality of service QOS support Eight transmit channels with round robin or fixed priority for transmit quality of service QOS support Ether Stats and 802 3 Stats RMON statistics gathering Transmit CRC generation selectable on a per ...

Page 14: ... to allow almost transparent operation of the MDIO interface with very little maintenance from the core processor The EMAC module provides an efficient interface between the processor and the networked community The EMAC on this device supports 10 Mbits second and 100 Mbits second in either half duplex or full duplex mode with hardware flow control and quality of service QOS support Figure 1 EMAC ...

Page 15: ...e EMAC intentionally generates an incorrect checksum by inverting the frame CRC so that the transmitted frame is detected as an error by the network 2 Architecture This section discusses the architecture and basic function of the EMAC MDIO module 2 1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802 3 specification as 2 5 MHz at 10 Mbps 25 MHz at 100 Mbps ...

Page 16: ... are placed in the system memory versus when they are placed in the EMAC s internal memory Cache performance is improved when the buffer descriptors are placed in internal memory However the EMAC throughput is better when the descriptors are placed in the local EMAC RAM 2 3 Signal Descriptions The DM36x DMSoC supports the MII interface for 10 100 Mbps operation 2 3 1 Media Independent Interface MI...

Page 17: ... Mbps operation and 25 MHz at 100 Mbps operation EMAC_RXD 3 0 I Receive data EMAC_RXD The receive data pins are a collection of 4 data signals comprising 4 bits of data MRDX0 is the least significant bit LSB The signals are synchronized by EMAC_RX_CLK and valid only when EMAC_RX_DV is asserted EMAC_RX_DV I Receive data valid EMAC_RX_DV The receive data valid signal indicates that the EMAC_RXD pins...

Page 18: ...r multicast including broadcast address When the destination EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 Source address This field contains the MAC address of the Ethernet port that transmits the frame to the Local Area Network Len 2 ...

Page 19: ...the frame 4 If the port detects signal energy from other ports while transmitting it stops transmitting its frame and instead transmits a 48 bit jam signal 5 After transmitting the jam signal the port enters an exponential backoff phase Specifically when transmitting a given frame after experiencing a number of collisions in a row for the frame the port chooses a random value that is dependent on ...

Page 20: ...ve packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data This field only has meaning when the buffer descriptor points to a buffer that actually contains data Buffer Length The buffer length is the actual number of valid packet data bytes stored in the buffer If the buffer is empty and waiting to re...

Page 21: ...ist to the corresponding HDP register Note that the last descriptor in the list must have its next pointer cleared to 0 This is the only way the EMAC has of detecting the end of the list So in the case where only a single descriptor is added its next descriptor pointer must be initialized to 0 The HDP must never be written to a second time while a previous list is active To add additional descript...

Page 22: ...nes whether or not an active interrupt actually interrupts the CPU In general the individual interrupts for different events from the EMAC and MDIO must be enabled in the EMAC control module and it also must be mapped in the ARM interrupt controller and enabled as a CPU interrupt If the system is configured properly the interrupt for a specific receive or transmit channel executes under the previo...

Page 23: ...iptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMAC_DSC_FLAG_SOP 0x80000000u defi...

Page 24: ...plication must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only checked on the first descriptor of a given packet where the start of packet SOP flag is set It can not be used to specify the offset of subsequent packet fragments Also since the buffer pointer may point to any byte aligned address this field m...

Page 25: ... the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC Note that this flag is valid on EOP descriptors only 2 6 4 10 Teardown Complete TDOWNCMPLT Flag This flag is used when a transmit queue is being torn down or aborted instead of allowing it to be transmitt...

Page 26: ...ed descriptor The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read In this latter case the receiver will halt the receive channel in question and the software application may restart it at that time The software can detect this case by checking for an end of queue EOQ condition flag on the updated packet descriptor when it is retur...

Page 27: ..._CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMATCH 0x00010000u 2 6 5 3 Buffer Offset This 16 bit field must be initialized to zero by the software application before adding the descriptor to a receive queue Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register When the offset register is set to a non zero value the received packet is written to the packet buffe...

Page 28: ...escriptors 2 6 5 8 Ownership OWNER Flag When set this flag indicates that the descriptor is currently owned by the EMAC This flag is set by the software application before adding the descriptor to the receive descriptor queue This flag is cleared by the EMAC once it is finished with a given set of descriptors associated with a received packet The flag is updated by the EMAC on SOP descriptor only ...

Page 29: ...he received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE 2 6 5 17 Overrun Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet was aborted due to a receive overrun 2 6 5 18 Code Error CODEERROR Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet contained a code error and ...

Page 30: ...dently of the CPU It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory Memory accesses to read or write the actual Ethernet packet data are protected by the EMAC s internal FIFOs A descriptor is a 16 byte memory structure that holds information about a single Ethernet packet buffer which may contain a full or partial Ethernet packet Thus wit...

Page 31: ...tor of the last packet processed by the application software 4 Write the MAC end of interrupt vector register MACEOIVECTOR in the EMAC module with a value of 2h to signal the end of the transmit interrupt processing 2 7 3 2 Receive Pulse Interrupt The EMAC control module receives the eight individual receive interrupts originating from the EMAC module one for each of the eight channels and combine...

Page 32: ...th a value of 3h to signal the end of the miscellaneous interrupt processing 2 7 4 Interrupt Pacing The receive and transmit pulse interrupts can be paced The receive threshold and miscellaneous interrupts can not be paced The interrupt pacing feature limits the number of interrupts to the CPU during a given period of time For heavily loaded systems in which interrupts can occur at a very high rat...

Page 33: ...on or interrupt the CPU once the operation has completed 2 8 1 MDIO Module Components The MDIO module Figure 9 interfaces to the PHY components through two MDIO pins MDCLK and MDIO and to the CPU through the EMAC control module and the configuration bus The MDIO module consists of the following logical components MDIO clock generator Global PHY detection and link state monitoring Active PHY monito...

Page 34: ...nected PHY does not require it Once the MDIO module is enabled the MDIO interface state machine continuously polls the PHY link status by reading the generic status register of all possible 32 PHY addresses and records the results in the MDIO PHY alive status register ALIVE and MDIO PHY link status register LINK The corresponding bit for the connected PHY 0 31 is set in ALIVE if the PHY responded ...

Page 35: ...termined by polling the GO bit in USERACCESSn for a 0 4 Completion of the operation sets the corresponding USERINTRAW bit 0 or 1 in the MDIO user command complete interrupt register USERINTRAW corresponding to USERACCESSn used If interrupts have been enabled on this bit using the MDIO user command complete interrupt mask set register USERINTMASKSET then the bit is also set in the MDIO user command...

Page 36: ...ocedure outlined in Section 2 8 2 3 Since the MDIO PHY alive status register ALIVE is used to initially select a PHY it is assumed that the PHY is acknowledging read operations It is possible that a PHY could become inactive at a future point in time An example of this would be a PHY that can have its MDIO addresses changed while the system is running It is not very likely but this condition can b...

Page 37: ...e transmit path includes transmit DMA engine transmit FIFO and MAC transmitter Statistics logic State RAM Interrupt controller Control registers and logic Clock and reset logic Figure 10 EMAC Module Block Diagram 2 9 1 1 Receive DMA Engine The receive DMA engine is the interface between the receive FIFO and the system core It interfaces to the CPU through the bus arbiter in the EMAC control module...

Page 38: ... 1518 bytes standard Ethernet packet size to be sent without the possibility of underrun The FIFO buffers data in preparation for transmission 2 9 1 7 MAC Transmitter The MAC transmitter formats frame data from the transmit FIFO and transmits the data using the CSMA CD access protocol The frame CRC can be automatically appended if required The MAC transmitter also detects transmission errors and p...

Page 39: ...em s internal or external memory For receive operations each 16 byte descriptor represents a free packet buffer or buffer fragment On both transmit and receive an Ethernet packet is allowed to span one or more memory fragments represented by one 16 byte descriptor per fragment In typical operation there is only one descriptor per receive buffer but transmit packets may be fragmented depending on t...

Page 40: ... based on the number of free buffers available Receive buffer flow control issues flow control collisions in half duplex mode and IEEE 802 3X pause frames for full duplex mode Receive buffer flow control is triggered when the number of free buffers in any enabled receive channel free buffer count register RXnFREEBUFFER is less than or equal to the receive channel flow control threshold register RX...

Page 41: ...e frame currently being transmitted The pause frame contains the maximum possible value for the pause time FFFFh The EMAC counts the receive pause frame time decrements FF00h to 0 and retransmits an outgoing pause frame if the count reaches 0 When the flow control request is removed the EMAC transmits a pause frame with a zero pause time to cancel the pause request Note that transmitted pause fram...

Page 42: ...ces delays into the normal transmission of frames delaying transmission attempts between stations reducing the probability of collisions occurring during heavy traffic as indicated by frame deferrals and collisions thereby increasing the chance of successful transmission When a frame is deferred suffers a single collision multiple collisions or excessive collisions the pacing counter is loaded wit...

Page 43: ...use time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer immediately expires The EMAC does not start the transmission of a new data frame any sooner than 512 bit times after a pause frame with a nonzero pause time has finished being received EMAC_RX_DV going inactive No transmission begins until the pause t...

Page 44: ...cast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE determines if broadcast frames are enabled or filtered If broadcast frames are enabled then they are copied to only a single channel selected by the RXBROADCH field in RXMBPENABLE The RXMULTEN bit in RXMBPENABLE determines if hash matching multicast frames are ...

Page 45: ...me length type value is equal to 81 00h the EMAC recognizes the frame as an Ethernet Encoded Tag Protocol Type The two octets immediately following the protocol type contain the 16 bit TCI field Bits 15 13 of the TCI field contain the received frames priority 0 to 7 The received frame is a low priority frame if the priority value is 0 to 3 the received frame is a high priority frame if the priorit...

Page 46: ...commanded teardown The read value is FFFF FFFCh if the interrupt was due to a teardown command 2 11 7 Receive Frame Classification Received frames are proper good frames if they are between 64 bytes and the value in the receive maximum length register RXMAXLEN bytes in length inclusive and contain no code align or CRC errors Received frames are long frames if their frame count exceeds the value in...

Page 47: ...le 4 Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred 0 1 0 0 0 Proper frames transferred to promiscuous channel 0 1 0 0 1 Proper undersized data frames transferred to promiscuous channel 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel 0 1 0 1 1 Proper undersized data and control frames...

Page 48: ...ns after starting the frame reception is filtered and the appropriate statistic s are incremented however the RXCEFEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment Table 5 shows how the overrun condition is handled for the middle of frame overrun Table 5 Middle of Frame Overrun Treatment Address Match RXCAFEN RXCEFEN Middle o...

Page 49: ...n completion pointer register TXnCP contains the value FFFF FFFCh The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value Channel teardown may be commanded on any channel at any time The host is informed of the teardown completion by the set teardown complete TDOWNCMPLT buffer descriptor bit The EMAC does not clear any channel enables due to a teardown command A teard...

Page 50: ...Considerations 2 15 1 Software Reset Considerations Peripheral clock and reset control is done through the Power and Sleep Controller PSC module included with the device For more on how the EMAC MDIO and EMAC control module are disabled or placed in reset at runtime from the registers located in the PSC module see Section 2 18 NOTE For proper operation both the EMAC and EMAC control module must be...

Page 51: ...g an interrupt retrigger count based on the peripheral clock PLL1 6 There is also an 8K block of RAM local to the EMAC that is used to hold packet buffer descriptors Note that although the EMAC control module and the EMAC module have slightly different functions in practice the type of maintenance performed on the EMAC control module is more commonly conducted from the EMAC module software as oppo...

Page 52: ...ms EmacControlRegs INTR_COUNT C_TX_IMAX 0x4 4 TX intt ms EmacControlRegs INT_CONTROL 0x30000 bit16 bit17 for enabling TX and Rx intt pacing EmacControlRegs INT_CONTROL 0x258 600 clocks of 150MHz in 4us time endif Initialize MDIO and EMAC Module Discussed later in this document Enable all the EMAC MDIO interrupts in the control module EmacControlRegs CONTROL C_RX_EN 0xff EmacControlRegs CONTROL C_T...

Page 53: ... Example 5 Example 5 MDIO Module Initialization Code define PCLK 99 Enable MDIO and setup divider MDIO_REGS CONTROL CSL_FMKT MDIO_CONTROL_ENABLE YES CSL_FMK MDIO_CONTROL_CLKDIV PCLK If the MDIO module is to operate on an interrupt basis the interrupts can be enabled at this time using the MDIO user command complete interrupt mask set register USERINTMASKSET for register access and the MDIO user PH...

Page 54: ...is to be enabled 7 Most device drivers open with no multicast addresses so clear the MAC address hash registers MACHASH1 and MACHASH2 to 0 8 Write the receive buffer offset register RXBUFFEROFFSET value typically zero 9 Initially clear all unicast channels by writing FFh to the receive unicast clear register RXUNICASTCLEAR If unicast is desired it can be enabled now by writing the receive unicast ...

Page 55: ...ng the corresponding bit in the receive interrupt mask set register RXINTMASKSET to 1 Each of the eight channel interrupts may be individually disabled by clearing the corresponding bit in the receive interrupt mask clear register RXINTMASKCLEAR to 0 The raw and masked receive interrupt status may be read from the receive interrupt status unmasked register RXINTSTATRAW and the receive interrupt st...

Page 56: ...ch each channel having a corresponding interrupt RXPENDn The receive interrupts are level interrupts that remain asserted until cleared by the CPU Each of the eight receive channel interrupts may be individually enabled by setting the corresponding bit in the receive interrupt mask set register RXINTMASKSET to 1 Each of the eight receive channel interrupts may be individually disabled by clearing ...

Page 57: ...ror bit can only be cleared by resetting the EMAC module in hardware The host error interrupt is enabled by setting the HOSTMASK bit in the MAC interrupt mask set register MACINTMASKSET to 1 The host error interrupt is disabled by clearing the appropriate bit in the MAC interrupt mask clear register MACINTMASKCLEAR to 0 The raw and masked host error interrupt status may be read by reading the MAC ...

Page 58: ... bit to USERINTMASKED write to clear 2 17 3 Proper Interrupt Processing All the interrupts signaled from the EMAC and MDIO modules are level driven so if they remain active their level remains constant the CPU core requires edge triggered interrupts In order to properly convert the level driven interrupt signal to an edge triggered signal the application software must make use of the interrupt con...

Page 59: ...he TMS320DM365 Digital Media System on Chip DMSoC ARM Subsystem Reference Guide SPRUFG5 2 19 Emulation Considerations NOTE For correct operation the EMAC and EMAC control module must both be suspended Thus the EMCONTROL and CMEMCONTROL registers must be configured alike EMAC emulation control is implemented for compatibility with other peripherals The SOFT and FREE bits in the emulation control re...

Page 60: ...nd Register Section 3 13 74h CMTXINTMAX Transmit Interrupts Per Millisecond Register Section 3 14 3 1 EMAC Control Module Identification and Version Register CMIDVER The identification and version register CMIDVER is shown in Figure 12 and described in Table 8 Figure 12 EMAC Control Module Identification and Version Register CMIDVER 31 16 EWIDENT R 2Eh 15 11 10 8 7 0 EWRTLVER EWMAJORVER EWMINORVER...

Page 61: ...ved R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 EMAC Control Module Emulation Control Register CMEMCONTROL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 SOFT Emulation soft bit This bit is used in conjunction with FREE bit to determine the emulation suspend mode This bit has no effect if FREE 1 0 Soft mo...

Page 62: ...le 11 EMAC Control Module Interrupt Control Register CMINTCTRL Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 18 Reserved 0 Reserved 17 16 INTPACEEN 0 3h Interrupt pacing enable Bit 16 1 enables Rx_Pulse Pacing 0 disables pacing Bit 17 1 enables Tx_Pulse Pacing 0 disables pacing 15 12 Reserved 0 Reserved 11 0 INTPRESCALE 0 7FFh Interrupt counter prescaler The number of pe...

Page 63: ...HPENDn is disabled Bit n 1 channel n receive threshold interrupt RXTHRESHPENDn is enabled 3 6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN The receive interrupt enable register CMRXINTEN is shown in Figure 17 and described in Table 13 Figure 17 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN 31 16 Reserved R 0 15 8 7 0 Reserved RXPULSEEN R 0 R W 0 LEGEND R W Read...

Page 64: ...alue after reset Table 14 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 TXPULSEEN n Transmit interrupt TXPENDn enable Each bit controls the corresponding channel n transmit interrupt Bit n 0 channel n transmit interrupt TXPENDn is disabled Bit n 1 channel n transmit interrupt TXPENDn is enabled 64 Ethern...

Page 65: ...MAC module statistics interrupt STATPEND enable 0 EMAC module statistics interrupt STATPEND is disabled 1 EMAC module statistics interrupt STATPEND is enabled 2 HOSTPENDINTEN EMAC module host error interrupt HOSTPEND enable 0 EMAC module host error interrupt HOSTPEND is disabled 1 EMAC module host error interrupt HOSTPEND is enabled 1 LINKINTEN MDIO module link change interrupt LINKINT enable 0 MD...

Page 66: ...nterrupt is not pending Bit n 1 channel n receive threshold interrupt is pending 3 10 EMAC Control Module Receive Interrupt Status Register CMRXINTSTAT The receive interrupt status register CMRXINTSTAT is shown in Figure 21and described in Table 17 Figure 21 EMAC Control Module Receive Interrupt Status Register CMRXINTSTAT 31 16 Reserved R 0 15 8 7 0 Reserved RXPULSEINTTSTAT R 0 R 0 LEGEND R Read ...

Page 67: ...lue after reset Table 18 EMAC Control Module Transmit Interrupt Status Register CMTXINTSTAT Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 TXPULSEINTTSTAT n Transmit interrupt status Each bit shows the status of the corresponding channel n transmit interrupt Bit n 0 channel n transmit interrupt is not pending Bit n 1 channel n transmit interrupt is pending 67 SPRUFI5B ...

Page 68: ...tistics interrupt STATPEND status 0 EMAC module statistics interrupt STATPEND is not pending 1 EMAC module statistics interrupt STATPEND is pending 2 HOSTPENDINTSTAT EMAC module host error interrupt HOSTPEND status 0 EMAC module host error interrupt HOSTPEND is not pending 1 EMAC module host error interrupt HOSTPEND is pending 1 LINKINTSTAT MDIO module link change interrupt LINKINT status 0 MDIO m...

Page 69: ...re 2 to 63 0 1h Reserved 3 14 EMAC Control Module Transmit Interrupts per Millisecond Register CMTXINTMAX The transmit interrupts per millisecond register CMTXINTMAX is shown in Figure 25and described in Table 21 Figure 25 EMAC Control Module Transmit Interrupts per Millisecond Register CMTXINTMAX 31 16 Reserved R 0 15 6 5 0 Reserved TXIMAX R 0 R W 0 LEGEND R W Read Write R Read only n value after...

Page 70: ...ASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 4 10 80h USERACCESS0 MDIO User Access Register 0 Section 4 11 84h USERPHYSEL0 MDIO User PHY Select Register 0 Section 4 12 88h USERACCESS1 MDIO User Access Register 1 Section 4 13 8Ch USERPHYSEL1 MDIO User PHY Select Register 1 Section 4 14 4 1 MDIO Version Register VERSION The MDIO version register VERSION is shown in Figur...

Page 71: ...module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDIO frame preambles 19 FAULT Fault indicator This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them This indicates a physical ...

Page 72: ...owledge the access 1 The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY 4 4 PHY Link Status Register LINK The PHY link status register LINK is shown in Figure 29 and described in Table 26 Figure 29 PHY Link Status Register LINK 31 16 LINK R 0 15 0 LINK R 0 LEGEND R Read only n value after reset Table 26 PHY Link Status Register LI...

Page 73: ...cription 31 2 Reserved 0 Reserved 1 0 LINKINTRAW 0 3h MDIO Link change event raw value When asserted a bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in the USERPHYSEL register LINKINTRAW 0 and LINKINTRAW 1 correspond to USERPHYSEL0 and USERPHYSEL1 respectively Writing a 1 will clear the event and writing a 0 has no effec...

Page 74: ...0 3h MDIO Link change interrupt masked value When asserted a bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in the USERPHYSEL register and the corresponding LINKINTENB bit was set LINKINTMASKED 0 and LINKINTMASKED 1 correspond to USERPHYSEL0 and USERPHYSEL1 respectively Writing a 1 will clear the event and writing a 0 has...

Page 75: ...ns Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTRAW 0 3h MDIO User command complete event bits When asserted a bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS register has completed USERINTRAW 0 and USERINTRAW 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing a 1 will clear the event and writing a 0 has no eff...

Page 76: ...NTMASKED 0 3h Masked value of MDIO User command complete interrupt When asserted a bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS register has completed and the corresponding USERINTMASKSET bit is set to 1 USERINTMASKED 0 and USERINTMASKED 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing a 1 will clear the interrupt and writin...

Page 77: ...0 USERINTMASKSET 0 3h MDIO user interrupt mask set for USERINTMASKED 1 0 respectively Setting a bit to 1 will enable MDIO user command complete interrupts for that particular USERACCESS register MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit is 0 USERINTMASKSET 0 and USERINTMASKSET 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing a 0 t...

Page 78: ... Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKCLEAR 0 3h MDIO user command complete interrupt mask clear for USERINTMASKED 1 0 respectively Setting a bit to 1 will disable further user command complete interrupts for that particular USERACCESS register USERINTMASKCLEAR 0 and USERINTMASKCLEAR 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing a 0 to this register has no e...

Page 79: ...d This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK 0 1 Acknowledge bit This bit is set if ...

Page 80: ...lies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is set to 0 0 Link change interru...

Page 81: ...This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK 0 1 Acknowledge bit This bit is set if th...

Page 82: ...tus is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for the PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is set to 0 0 Link change interrupts are disabled 1...

Page 83: ...cuous Channel Enable Register Section 5 21 104h RXUNICASTSET Receive Unicast Enable Set Register Section 5 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section 5 23 10Ch RXMAXLEN Receive Maximum Length Register Section 5 24 110h RXBUFFEROFFSET Receive Buffer Offset Register Section 5 25 114h RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register Section 5 26 120h RX0FLOWTH...

Page 84: ... DMA Head Descriptor Pointer Register Section 5 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 5 47 624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section 5 47 628h RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register Section 5 47 62Ch RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register Section 5 47 630h RX4HDP Receive Channel 4...

Page 85: ...nsmit Frames Register Section 5 50 18 248h TXCOLLISION Transmit Collision Frames Register Section 5 50 19 24Ch TXSINGLECOLL Transmit Single Collision Frames Register Section 5 50 20 250h TXMULTICOLL Transmit Multiple Collision Frames Register Section 5 50 21 254h TXEXCESSIVECOLL Transmit Excessive Collision Frames Register Section 5 50 22 258h TXLATECOLL Transmit Late Collision Frames Register Sec...

Page 86: ...at TXMAJORVER TXMINORVER 02h Current transmit major version value 7 0 TXMINORVER Transmit minor version value Revisions are indicated by a revision code taking the format TXMAJORVER TXMINORVER 0Ch Current transmit minor version value 5 2 Transmit Control Register TXCONTROL The transmit control register TXCONTROL is shown in Figure 41 and described in Table 39 Figure 41 Transmit Control Register TX...

Page 87: ...3 Reserved 0 Reserved 2 0 TXTDNCH 0 7h Transmit teardown channel The transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h Teardown transmit channel 1 2h Teardown transmit channel 2 3h Teardown transmit channel 3 4h Teardown transmit channel 4 5h Teardown transmit channel 5 6h ...

Page 88: ...eld Descriptions Bit Field Value Description 31 16 RXIDENT Receive identification value Ch Current receive identification value 15 8 RXMAJORVER Receive major version value Revisions are indicated by a revision code taking the format RXMAJORVER RXMINORVER 02h Current receive major version value 7 0 RXMINORVER Receive minor version value Revisions are indicated by a revision code taking the format R...

Page 89: ...ardown Register RXTEARDOWN 31 16 Reserved R 0 15 3 2 0 Reserved RXTDNCH R 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 43 Receive Teardown Register RXTEARDOWN Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RXTDNCH 0 7h Receive teardown channel The receive channel teardown is commanded by writing the encoded value of the receive channel to be torn...

Page 90: ...us Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND raw interrupt read before mask 6 TX6PEND 0 1 TX6PEND raw interrupt read before mask 5 TX5PEND 0 1 TX5PEND raw interrupt read before mask 4 TX4PEND 0 1 TX4PEND raw interrupt read before mask 3 TX3PEND 0 1 TX3PEND raw interrupt read before mask 2 TX2PEND 0 1 TX2PEND raw int...

Page 91: ...eset Table 45 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND masked interrupt read 6 TX6PEND 0 1 TX6PEND masked interrupt read 5 TX5PEND 0 1 TX5PEND masked interrupt read 4 TX4PEND 0 1 TX4PEND masked interrupt read 3 TX3PEND 0 1 TX3PEND masked interrupt read 2 TX2PEND 0 1 TX2PEND masked interru...

Page 92: ... 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 TX4MASK 0 1 Transmit channel 4 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 3 TX3MASK 0 1 Transmit channel 3 interrupt mask se...

Page 93: ... 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 4 TX4MASK 0 1 Transmit channel 4 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 3 TX3MASK 0 1 Transmit channel 3 interrup...

Page 94: ...it channel 0 15 8 RXTHRESHPEND 0 FFh Receive threshold channels 0 7 interrupt pending RXTHRESHPENDn status bit Bit 8 is receive channel 0 7 0 RXPEND 0 FFh Receive channels 0 7 interrupt pending RXPENDn status bit Bit 0 is receive channel 0 5 12 MAC End Of Interrupt Vector Register MACEOIVECTOR The MAC end of interrupt vector register MACEOIVECTOR is shown in Figure 51 and described in Table 49 Fig...

Page 95: ...s Unmasked Register RXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND 0 1 RX7PEND raw interrupt read before mask 6 RX6PEND 0 1 RX6PEND raw interrupt read before mask 5 RX5PEND 0 1 RX5PEND raw interrupt read before mask 4 RX4PEND 0 1 RX4PEND raw interrupt read before mask 3 RX3PEND 0 1 RX3PEND raw interrupt read before mask 2 RX2PEND 0 1 RX2PEND raw inte...

Page 96: ...eset Table 51 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND 0 1 RX7PEND masked interrupt read 6 RX6PEND 0 1 RX6PEND masked interrupt read 5 RX5PEND 0 1 RX5PEND masked interrupt read 4 RX4PEND 0 1 RX4PEND masked interrupt read 3 RX3PEND 0 1 RX3PEND masked interrupt read 2 RX2PEND 0 1 RX2PEND masked interrup...

Page 97: ... to enable interrupt a write of 0 has no effect 6 RX6MASK 0 1 Receive channel 6 mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 RX5MASK 0 1 Receive channel 5 mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 RX4MASK 0 1 Receive channel 4 mask set bit Write 1 to enable interrupt a write of 0 has no effect 3 RX3MASK 0 1 Receive channel 3 mask set bit Write 1...

Page 98: ...to disable interrupt a write of 0 has no effect 6 RX6MASK 0 1 Receive channel 6 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 RX5MASK 0 1 Receive channel 5 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 4 RX4MASK 0 1 Receive channel 4 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 3 RX3MASK 0 1 Receive channel 3 mask clear ...

Page 99: ...upt STATPEND raw interrupt read before mask 5 18 MAC Interrupt Status Masked Register MACINTSTATMASKED The MAC interrupt status masked register MACINTSTATMASKED is shown in Figure 57 and described in Table 55 Figure 57 MAC Interrupt Status Masked Register MACINTSTATMASKED 31 16 Reserved R 0 15 2 1 0 Reserved HOSTPEND STATPEND R 0 R 0 R 0 LEGEND R Read only n value after reset Table 55 MAC Interrup...

Page 100: ...rite of 0 has no effect 5 20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR The MAC interrupt mask clear register MACINTMASKCLEAR is shown in Figure 59 and described in Table 57 Figure 59 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 31 16 Reserved R 0 15 2 1 0 Reserved HOSTMASK STATMASK R 0 R W1C 0 R W1C 0 LEGEND R Read only R W Read Write W1C Write 1 to clear write of 0 has no effect n va...

Page 101: ...e no buffer chaining bit 0 Received frames can span multiple buffers 1 The Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size All remaining frame data after the first buffer is discarded The buffer descriptor buffer length field will contain the entire frame byte count up to 65535 bytes 27 25 Reserved 0 Reserved 24 RXCMFEN Receive copy MAC contr...

Page 102: ...es 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7 to receive promiscuous frames 15 14 Reserved 0 Reserved 13 RXBROADEN Receive broadcast enable Enable received broadcast frames to be copied to the channel selected by RXBROADCH bits 0 Broadcast frames are filtered 1 Broadcast f...

Page 103: ...annel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast frames 5h Select channel 5 to receive multicast frames 6h Select channel 6 to receive multicast frames 7h Select channel 7 to receive multicast frames 103 SPRUFI5B March 2009 Revised December 2010 Ethernet Media Access Controll...

Page 104: ...1 Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN 0 1 Receive channel 5 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 4 RXCH4EN 0 1 Receive channel 4 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 3 RXCH3EN 0 1 Receive channel 3 unicast enable set b...

Page 105: ...effect 6 RXCH6EN 0 1 Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN 0 1 Receive channel 5 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 4 RXCH4EN 0 1 Receive channel 4 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 3 RXCH3EN 0 1 Receive channel 3 unicast enable clear bit ...

Page 106: ...FFEROFFSET is shown in Figure 64 and described in Table 62 Figure 64 Receive Buffer Offset Register RXBUFFEROFFSET 31 16 Reserved R 0 15 0 RXBUFFEROFFSET R W 0 LEGEND R Read only R W Read Write n value after reset Table 62 Receive Buffer Offset Register RXBUFFEROFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 RXBUFFEROFFSET 0 FFFFh Receive buffer offset value Th...

Page 107: ...ity incoming frames This field should remain 0 if no filtering is desired 5 27 Receive Channel 0 7 Flow Control Threshold Register RXnFLOWTHRESH The receive channel 0 7 flow control threshold register RXnFLOWTHRESH is shown in Figure 66 and described in Table 64 Figure 66 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH 31 16 Reserved R 0 15 8 7 0 Reserved RXnFLOWTHRESH R 0 R W 0 LE...

Page 108: ...ERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets if enabled This is a write to increment field This field rolls over to 0 on overflow If hardware flow control or QOS is used the host must initialize this field to the num...

Page 109: ...acket processing 1 EMAC writes the Receive ownership bit to 1 at the end of packet processing If you do not use the ownership mechanism you can set this mode to preclude the necessity of software having to set this bit each time the buffer descriptor is used 12 RXFIFOFLOWEN Receive FIFO flow control enable bit 0 Receive flow control is disabled Full duplex mode no outgoing pause frames are sent 1 ...

Page 110: ...able bit 0 Receive flow control is disabled Half duplex mode no flow control generated collisions are sent Full duplex mode no outgoing pause frames are sent 1 Receive flow control is enabled Half duplex mode collisions are initiated when receive buffer flow control is triggered Full duplex mode outgoing pause frames are sent when receive flow control is triggered 2 Reserved 0 Reserved 1 LOOPBACK ...

Page 111: ...t in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer descriptor pointer without EOP 4h Zero buffer pointer 5h Zero buffer length 6h Packet length error sum of buffers is less than packet length 19 Reserved 0 Reserved 18 16 TXERRCH 0 7h Transmit host error channel These bits indicate which transmit channel the host error occurred on This field is cleared to 0 on a host read 0 Th...

Page 112: ...abled and that at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the RXFILTERLOWTHRESH value 0 Receive quality of service is disabled 1 Receive quality of service is enabled 1 RXFLOWACT Receive flow control active bit When asserted at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the channel s corresponding RXnFILTERTHRESH value 0 Receive flow...

Page 113: ... Read Write R Read only n value after reset Table 69 FIFO Control Register FIFOCONTROL Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reserved 22 16 RXFIFOFLOWTHRESH 0 3Fh Receive FIFO flow control threshold Occupancy of the receive FIFO when receive FIFO flow control is triggered if enabled The default value is 2h which means that receive FIFO flow control is triggered when the o...

Page 114: ...register SOFTRESET is shown in Figure 73 and described in Table 71 Figure 73 Soft Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved SOFTRESET R 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 71 Soft Reset Register SOFTRESET Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 SOFTRESET Software reset Writing a 1 to this bit causes the EMAC logic ...

Page 115: ... Bytes Register MACSRCADDRHI The MAC source address high bytes register MACSRCADDRHI is shown in Figure 75 and described in Table 73 Figure 75 MAC Source Address High Bytes Register MACSRCADDRHI 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R W 0 R W 0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R W 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 73 MAC Source Address High Bytes Register MACSRCADDR...

Page 116: ... is shown in Figure 76 and described in Table 74 Figure 76 MAC Hash Address Register 1 MACHASH1 31 16 MACHASH1 R W 0 15 0 MACHASH1 R W 0 LEGEND R Read only R W Read Write n value after reset Table 74 MAC Hash Address Register 1 MACHASH1 Field Descriptions Bit Field Value Description 31 0 MACHASH1 0 FFFF FFFFh Least significant 32 bits of the hash table corresponding to hash values 0 to 31 If a has...

Page 117: ... time after the collision 5 40 Transmit Pacing Algorithm Test Register TPACETEST The transmit pacing algorithm test register TPACETEST is shown in Figure 79 and described in Table 77 Figure 79 Transmit Pacing Algorithm Test Register TPACETEST 31 16 Reserved R 0 15 5 4 0 Reserved PACEVAL R 0 R 0 LEGEND R Read only n value after reset Table 77 Transmit Pacing Algorithm Test Register TPACETEST Field ...

Page 118: ...ements to 0 then another outgoing pause frame is sent and the load decrement process is repeated 5 42 Transmit Pause Timer Register TXPAUSE The transmit pause timer register TXPAUSE is shown in Figure 81 and described in Table 79 Figure 81 Transmit Pause Timer Register TXPAUSE 31 16 Reserved R 0 15 0 PAUSETIMER R 0 LEGEND R Read only n value after reset Table 79 Transmit Pause Timer Register TXPAU...

Page 119: ...d and will not be used in determining whether or not an incoming packet matches or is filtered 1 Address location is valid and will be used in determining whether or not an incoming packet matches or is filtered 19 MATCHFILT Match or filter bit 0 The address will be used if the VALID bit is set to determine if the incoming packet address should be filtered 1 The address will be used if the VALID b...

Page 120: ...ast addresses are represented in the address table 5 45 MAC Index Register MACINDEX The MAC index register MACINDEX is shown in Figure 84 and described in Table 82 Figure 84 MAC Index Register MACINDEX 31 16 Reserved R 0 15 3 2 0 Reserved MACINDEX R 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 82 MAC Index Register MACINDEX Field Descriptions Bit Field Value Description 31 3...

Page 121: ...ialize these locations to 0 on reset 5 47 Receive Channel 0 7 DMA Head Descriptor Pointer Register RXnHDP The receive channel 0 7 DMA head descriptor pointer register RXnHDP is shown in Figure 86 and described in Table 84 Figure 86 Receive Channel n DMA Head Descriptor Pointer Register RXnHDP 31 16 RXnHDP R W x 15 0 RXnHDP R W x LEGEND R W Read Write n value after reset x value is indeterminate af...

Page 122: ... if the interrupt should be deasserted 5 49 Receive Channel 0 7 Completion Pointer Register RXnCP The receive channel 0 7 completion pointer register RXnCP is shown in Figure 88 and described in Table 86 Figure 88 Receive Channel n Completion Pointer Register RXnCP 31 16 RXnCP R W x 15 0 RXnCP R W x LEGEND R W Read Write n value after reset x value is indeterminate after reset Table 86 Receive Cha...

Page 123: ... frames received on the EMAC A good frame is defined as having all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no CRC error alignment error or code error See Section 2 6 5 for definitions of alignment code and CRC errors Overruns have no effect on this statis...

Page 124: ...Errors Register RXALIGNCODEERRORS The total number of frames received on the EMAC that experienced an alignment error or code error Such a frame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had either an alignment error or a code error...

Page 125: ...ing Any data frame address matching does not matter Was less than 64 bytes long Had a CRC error alignment error or code error Was not the result of a collision caused by half duplex collision based flow control See Section 2 6 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 5 50 11 Filtered Receive Frames Register RXFILTERED The total number of frames r...

Page 126: ...ess or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no CRC error alignment error or code error See Section 2 6 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 5 50 14 Good Transmit Frames Register TXGOODFRAMES The total number of good frames transmitted on the EMAC A good frame is defined as having all of the followin...

Page 127: ...l frame has all of the following Was destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced a collision A jam sequence is sent for every non late collision so this statistic increments on each occasion if a frame experiences multiple collisions and increments on late collisions When the EMAC is in half duplex mode flow control is active...

Page 128: ...his statistic 5 50 24 Transmit Underrun Error Register TXUNDERRUN The number of frames sent by the EMAC that experienced FIFO underrun Late collisions CRC errors carrier loss and underrun have no effect on this statistic 5 50 25 Transmit Carrier Sense Errors Register TXCARRIERSENSE The total number of frames on the EMAC that experienced carrier loss Such a frame is defined as having all of the fol...

Page 129: ...er of 256 byte to 511 byte frames received and transmitted on the EMAC Such a frame is defined as having all of the following Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 256 bytes to 511 bytes long CRC errors alignment code errors underruns and overruns do ...

Page 130: ...it cell FIFO full or no DMA buffer available at the start of the frame CRC errors alignment errors and code errors have no effect on this statistic 5 50 35 Receive FIFO or DMA Middle of Frame Overruns Register RXMOFOVERRUNS The total number of frames received on the EMAC that had either a FIFO or DMA middle of frame MOF overrun An MOF overrun frame is defined as having all of the following Was any...

Page 131: ...only be used when all of the following are true The physical medium is capable of supporting simultaneous transmission and reception without interference There are exactly two stations connected with a full duplex point to point link As there is no contention for use of a shared medium the multiple access that is CSMA CD algorithms are unnecessary Both stations on the LAN are capable of and have b...

Page 132: ...in Mb s medium type maximum segment length 100m The definitions for the technologies mentioned in this document are in Table 87 Table 87 Physical Layer Definitions Term Definition 10Base T IEEE 802 3 Physical Layer specification for a 10 Mb s CSMA CD local area network over two pairs of twisted pair telephone wire 100Base T IEEE 802 3 Physical Layer specification for a 100 Mb s CSMA CD local area ...

Page 133: ...previous version of this document Table 88 Document Revision History Reference Additions Modifications Deletions Section 1 3 Changed fourth paragraph 133 SPRUFI5B March 2009 Revised December 2010 Revision History Submit Documentation Feedback 2009 2010 Texas Instruments Incorporated ...

Page 134: ...ch statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications o...

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