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Ethernet Media Access Controller (EMAC) Registers
5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in
Figure 65
and described in
Table 63
.
Figure 65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXFILTERTHRESH
R-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 63. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXFILTERTHRESH
0-FFh
Receive filter low threshold. These bits contain the free buffer count threshold value for filtering
low priority incoming frames. This field should remain 0, if no filtering is desired.
5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)
The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in
Figure 66
and
described in
Table 64
.
Figure 66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXnFLOWTHRESH
R-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 64. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXnFLOWTHRESH
0-FFh
Receive flow threshold. These bits contain the threshold value for issuing flow control on
incoming frames for channel n (when enabled).
107
SPRUFI5B – March 2009 – Revised December 2010
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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