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Architecture
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2.7.3.3
Receive Threshold Pulse Interrupt
The EMAC control module receives the eight individual receive threshold interrupts originating from the
EMAC module, one for each of the eight channels, and combines them into a single receive threshold
pulse interrupt to the CPU. This receive threshold pulse interrupt is not paced. The eight individual receive
threshold pending interrupt(s) are selected at the EMAC control module level, by setting one or more bits
in the EMAC control module receive threshold interrupt enable register (CMRXTHRESHINTEN). The
masked interrupt status can be read in the EMAC control module receive threshold interrupt status
register (CMRXTHRESHINTSTAT).
Upon reception of a receive threshold pulse interrupt, the ISR performs the following:
1. Read CMRXTHRESHINTSTAT to determine which channel(s) caused the interrupt.
2. Process received packets in order to add more buffers to any channel that is below the threshold
value.
3. Write the appropriate CPGMAC receive channel n completion pointer register(s) (RXnCP) with the
address of the last buffer descriptor of the last packet processed by the application software.
4. Write the MAC end of interrupt vector register (MACEOIVECTOR) in the EMAC module with a value of
0 to signal the end of the receive threshold interrupt processing.
2.7.3.4
Miscellaneous Pulse Interrupt
The EMAC control module receives the STATPEND and HOSTPEND interrupts from the EMAC module
and the MDIO_LINKINT and MDIO_USERINT interrupts from the MDIO module. The EMAC control
module combines these four interrupts into a single miscellaneous pulse interrupt to the CPU. This
miscellaneous interrupt is not paced. The four individual interrupts are selected at the EMAC control
module level, by setting one or more bits in the EMAC control module miscellaneous interrupt enable
register (CMMISCINTEN). The masked interrupt status can be read in the EMAC control module
miscellaneous interrupt status register (CMMISCINTSTAT).
Upon reception of a miscellaneous pulse interrupt, the ISR performs the following:
1. Read CMMISCINTSTAT to determine which of the four condition(s) caused the interrupt.
2. Process those interrupts accordingly.
3. Write the MAC end of interrupt vector register (MACEOIVECTOR) in the EMAC module with a value of
3h to signal the end of the miscellaneous interrupt processing.
2.7.4
Interrupt Pacing
The receive and transmit pulse interrupts can be paced. The receive threshold and miscellaneous
interrupts can not be paced. The interrupt pacing feature limits the number of interrupts to the CPU during
a given period of time. For heavily loaded systems in which interrupts can occur at a very high rate, the
performance benefit is significant due to minimizing the overhead associated with servicing each interrupt.
The receive and transmit pulse interrupts contain a separate interrupt pacing sub-blocks. Each sub-block
is disabled by default allowing the selected interrupt inputs to pass-through unaffected.
The interrupt pacing module counts the number of interrupts that occur over a 1 ms interval of time. At the
end of each 1 ms interval, the current number of interrupts is compared with a target number of interrupts
(specified by the associated EMAC control module interrupts per millisecond registers, CMTXINTMAX and
CMRXINTMAX). Based on the results of the comparison, the length of time during which interrupts are
blocked is dynamically adjusted. The 1 ms interval is derived from a 4
m
s pulse that is created from a
prescale counter whose value is set in the INTPRESCALE field of the EMAC control module interrupt
control register (CMINTCTRL). This INTPRESCALE value should be written with the number of peripheral
clock periods in 4
m
s. The pacing timer determines the interval during which interrupts are blocked and
decrements every 4
m
s. It is reloaded each time a zero count is reached. The value loaded into the pacing
timer is calculated by hardware every 1 ms, according to the dynamic algorithm in the hardware.
If the rate of transmit pulse interrupt inputs is much less than the target transmit pulse interrupt rate
specified in CMTXINTMAX, then the interrupts are not blocked to the CPU. If the transmit pulse interrupt
rate is greater than the specified target rate in CMTXINTMAX, the interrupt is paced at the rate specified
in this register, which should be written with a value between 2 and 63 inclusive, indicating the target
number of interrupts per 1 ms going to the CPU. Similarly, the number of receive interrupt pulses to the
CPU is also separately controlled.
32
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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