![background image](http://html1.mh-extra.com/html/texas-instruments/tms320dm36-series/tms320dm36-series_user-manual_1095290026.webp)
Architecture
www.ti.com
2.6.5
Receive Buffer Descriptor Format
A receive (RX) buffer descriptor (
Figure 7
) is a contiguous block of four 32-bit data words aligned on a
32-bit boundary that describes a packet or a packet fragment.
Example 2
shows the receive buffer
descriptor described by a C structure.
2.6.5.1
Next Descriptor Pointer
This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive
queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero,
then the current buffer is the last buffer in the queue. The software application must set this value prior to
adding the descriptor to the active receive list. This pointer is not altered by the EMAC.
The value of pNext should never be altered once the descriptor is in an active receive queue, unless its
current value is NULL. If the pNext pointer is initially NULL, and more empty buffers can be added to the
pool, the software application may alter this pointer to point to a newly appended descriptor. The EMAC
will use the new pointer value and proceed to the next descriptor unless the pNext value has already been
read. In this latter case, the receiver will halt the receive channel in question, and the software application
may restart it at that time. The software can detect this case by checking for an end of queue (EOQ)
condition flag on the updated packet descriptor when it is returned by the EMAC.
2.6.5.2
Buffer Pointer
The buffer pointer is the byte-aligned memory address of the memory buffer associated with the buffer
descriptor. The software application must set this value prior to adding the descriptor to the active receive
list. This pointer is not altered by the EMAC.
Figure 7. Receive Buffer Descriptor Format
Word 0
31
0
Next Descriptor Pointer
Word 1
31
0
Buffer Pointer
Word 2
31
16 15
0
Buffer Offset
Buffer Length
Word 3
31
30
29
28
27
26
25
24
SOP
EOP
OWNER
EOQ
TDOWNCMPLT
PASSCRC
JABBER
OVERSIZE
23
22
21
20
19
18
17
16
FRAGMENT
UNDERSIZED
CONTROL
OVERRUN
CODEERROR
ALIGNERROR
CRCERROR
NOMATCH
15
0
Packet Length
26
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
Submit Documentation Feedback
© 2009–2010, Texas Instruments Incorporated