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EMAC Control Module Registers
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3.7
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
The transmit interrupt enable register (CMTXINTEN) is shown in
Figure 18
and described in
Table 14
.
Figure 18. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
31
16
Reserved
R-0
15
8
7
0
Reserved
TXPULSEEN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
TXPULSEEN[n]
Transmit interrupt (TXPENDn) enable. Each bit controls the corresponding channel n transmit
interrupt.
Bit n = 0,channel n transmit interrupt (TXPENDn) is disabled.
Bit n = 1, channel n transmit interrupt (TXPENDn) is enabled.
64
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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