2.16 Power Management
2.17 Emulation Considerations
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Power Management
The EDMA3 (EDMA3CC and EDMA3TC) can be placed in reduced-power modes to conserve power
during periods of low activity. The power management of the peripheral is controlled by the device Power
and Sleep Controller (PSC). The PSC acts as a master controller for power management for all
peripherals on the device. For detailed information on power management procedures using the PSC, see
the
TMS320DM357 DMSoC ARM Subsystem Reference Guide
(
).
The EDMA3 controller can be idled on receiving a clock stop request from the PSC. The requests to
EDMA3CC and EDMA3TC are separate. In general, you should verify that there are no pending activities
in the EDMA3 controller before issuing a clock stop request via PSC.
The EDMA3CC checks for the following conditions:
•
No pending DMA/QDMA events
•
No outstanding events in the event queues
•
Transfer request processing logic is not active
•
No completion requests outstanding (early or normal completion)
•
No configuration bus requests in progress
The first four conditions are software readable by the channel controller status register (CCSTAT) in the
EDMA3CC.
Similarly, from the EDMA3TC perspective, you should check that there are no outstanding TRs that are
getting processed and essentially the read/write controller is not busy processing a TR. The activity of
EDMA3TC logic is read in TCSTAT for each EDMA3TC..
It is generally recommended to first disable the EDMA3CC and then the EDMA3TC(s) to put the EDMA3
controller in reduced-power modes.
Additionally, when EDMA3 is involved in servicing a peripheral and it is required to power-down both the
peripheral and the EDMA, the recommended sequence is to first disable the peripheral, then disable the
DMA channel associated with the peripheral (clearing the EER/EERH bit for the channel), then disable the
EDMA3CC, and finally disable the EDMA3TC(s).
During debug when using the emulator, the CPU(s) may be halted on an execute packet boundary for
single-stepping, benchmarking, profiling, or other debug purposes. During an emulation halt, the EDMA3
channel controller and transfer controller operations continue. Events continue to be latched and
processed and transfer requests continue to be submitted and serviced.
Since EDMA3 is involved in servicing multiple master and slave peripherals, it is not feasible to have an
independent behavior of the EDMA3 for emulation halts. EDMA3 functionality would be coupled with the
peripherals it is servicing, which might have different behavior during emulation halts. For example, if a
ASP is halted during an emulation access (FREE = 0 and SOFT = 0 or 1 in ASP registers), the ASP stops
generating the ASP receive or transmit events (REVT or XEVT) to the EDMA. From the point of view of
the ASP, the EDMA3 is suspended, but other peripherals (for example, a timer) still assert events and will
be serviced by the EDMA.
SPRUG34 – November 2008
EDMA3 Architecture
63
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