Texas Instruments TMS320DM357, User Manual

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4.3.3 Region Access Enable Registers
4.3.3.1 DMA Region Access Enable for Region m (DRAEm)
EDMA3 Channel Controller Control Registers
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The region access enable register group consists of the DMA access enable registers (DRAE m and
DRAEH m ) and the QDMA access enable registers (QRAE m ). Where m is the number of shadow regions
in the EDMA3CC memory map for a device. You can configure these registers to assign ownership of
DMA/QDMA channels to a particular shadow region.
The DMA region access enable register for shadow region m (DRAE m /DRAEH m ) is programmed to allow
or disallow read/write accesses on a bit-by-bit bases for all DMA registers in the shadow region m view of
the DMA channel registers. See the EDMA3CC register memory map for a list of all the DMA channel and
interrupt registers mapped in the shadow region view. Additionally, the DRAE
m /DRAEH m configuration
determines completion of which DMA channels will result in assertion of the shadow region m DMA
completion interrupt (see Section 2.9 ).
The DRAE m is shown in Figure 4-24 and described in Table 4-27 . The DRAEH m is shown in Figure 4-25
and described in Table 4-27 .
Figure 4-24. DMA Region Access Enable Register for Region m (DRAEm)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; - n = value after reset
Figure 4-25. DMA Region Access Enable High Register for Region m (DRAEHm)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; - n = value after reset
Table 4-27. DMA Region Access Enable Registers for Region m (DRAEm/DRAEHm)
Field Descriptions
Bit Field Value Description
31-0 E n DMA region access enable for bit n /channel n in region m .
0 Accesses via region m address space to bit n in any DMA channel register are not allowed. Reads return
0 on bit n and writes do not modify the state of bit n . Enabled interrupt bits for bit n do not contribute to the
generation of a transfer completion interrupt for shadow region m .
1 Accesses via region m address space to bit n in any DMA channel register are allowed. Reads return the
value from bit n and writes modify the state of bit n . Enabled interrupt bits for bit n contribute to the
generation of a transfer completion interrupt for shadow region m .
Registers 110 SPRUG34 – November 2008
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