Texas Instruments TMS320DM357, User Manual

Page: 116 / 167

4.3.5 DMA Channel Registers
4.3.5.1 Event Registers (ER, ERH)
EDMA3 Channel Controller Control Registers
www.ti.com
Table 4-32. EDMA3CC Status Register (CCSTAT) Field Descriptions (continued)
Bit Field Value Description
3 WSTATACTV Write status interface active.
0 Write status req is idle and write status fifo is idle.
1 Either the write status request is active or additional write status responses are pending in the write
status fifo.
2 TRACTV Transfer request active.
0 Transfer request processing/submission logic is inactive.
1 Transfer request processing/submission logic is active.
1 QEVTACTV QDMA event active.
0 No enabled QDMA events are active within the EDMA3CC.
1 At least one enabled QDMA event (QER) is active within the EDMA3CC.
0 EVTACTV DMA event active.
0 No enabled DMA events are active within the EDMA3CC.
1 At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC.
The following sets of registers pertain to the 64 DMA channels. The 64 DMA channels consist of a set of
registers (with exception of DMAQNUM
n ) that each have 64 bits and the bit position of each register
matches the DMA channel number. Each register is named with the format reg_name that corresponds to
DMA channels 0 through 31 and reg_name_High that corresponds to DMA channels 32 through 64.
For example, the event register (ER) corresponds to DMA channel 0 through 31 and the event register
high register (ERH) corresponds to DMA channel 32 through 63. The register is typically called the event
register.
The DMA channel registers are accessible via read/writes to the global address range. They are also
accessible via read/writes to the shadow address range. The read/write ability to the registers in the
shadow region are controlled by the DMA region access registers (DRAE
m /DRAEH m ). The registers are
described in Section 4.3.3.1 and the details for shadow region/global region usage is explained in
Section 2.7 .
All external events are captured in the event register (ER/ERH). The events are latched even when the
events are not enabled. If the event bit corresponding to the latched event is enabled (EER.E
n /EERH.E n
= 1), then the event is evaluated by the EDMA3CC logic for an associated transfer request submission to
the transfer controllers. The event register bits are automatically cleared (ER.E
n /ERH.E n = 0) once the
corresponding events are prioritized and serviced. If ER.E n /ERH.E n are already set and another event is
received on the same channel/event, then the corresponding event is latched in the event miss register
(EMR.E
n /EMRH.E n ), provided that the event was enabled (EER.E n /EERH.E n = 1).
Event n can be cleared by the CPU writing a 1 to corresponding event bit in the event clear register
(ECR/ECRH). The setting of an event is a higher priority relative to clear operations (via hardware or
software). If set and clear conditions occur concurrently, the set condition wins. If the event was previously
set, then EMR/EMRH would be set since an event is lost. If the event was previously clear, then the event
remains set and is prioritized for submission to the event queues.
Table 2-5 provides the type of synchronization events and the EDMA3CC channels associated to each of
these external events.
The ER is shown in Figure 4-31 and described in Table 4-33 . The ERH is shown in Figure 4-32 and
described in Table 4-34 .
Registers 116 SPRUG34 – November 2008
Submit Documentation Feedback