Texas Instruments TMS320DM357, User Manual

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3.4.4 Ping-Pong Buffering
3.4.4.1 Synchronization with the CPU
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Peripheral Servicing Example
Although the previous configuration allows the EDMA3 to service a peripheral continuously, it presents a
number of restrictions to the CPU. Since the input and output buffers are continuously being filled/emptied,
the CPU must match the pace of the EDMA3 very closely in order to process the data. The EDMA3
receive data must always be placed in memory before the CPU accesses it, and the CPU must provide
the output data before the EDMA3 transfers it. Though not impossible, this is an unnecessary challenge. It
is particularly difficult in a 2-level cache scheme.
Ping-pong buffering is a simple technique that allows the CPU activity to be distanced from the EDMA3
activity. This means that there are multiple (usually two) sets of data buffers for all incoming and outgoing
data streams. While the EDMA3 transfers the data into and out of the ping buffers, the CPU manipulates
the data in the pong buffers. When both CPU and EDMA3 activity completes, they switch. The EDMA3
then writes over the old input data and transfers the new output data.
Figure 3-14 shows the ping-pong
scheme for this example.
To change the continuous operation example, such that a ping-pong buffering scheme is used, the DMA
channels need only a moderate change. Instead of one parameter set, there are two; one for transferring
data to/from the ping buffers and one for transferring data to/from the pong buffers. As soon as one
transfer completes, the channel loads the PaRAM set for the other and the data transfers continue.
Figure 3-15 shows the DMA channel configuration required.
Each channel has two parameter sets, ping and pong. The DMA channel is initially loaded with the ping
parameters (
Figure 3-15 ). The link address for the ping set is set to the PaRAM offset of the pong
parameter set ( Figure 3-16 ). The link address for the pong set is set to the PaRAM offset of the ping
parameter set ( Figure 3-17 ). The channel options, count values, and index values are all identical between
the ping and pong parameters for each channel. The only differences are the link address provided and
the address of the data buffer.
In order to utilize the ping-pong buffering technique, the system must signal the CPU when to begin to
access the new data set. After the CPU finishes processing an input buffer (ping), it waits for the EDMA3
to complete before switching to the alternate (pong) buffer. In this example, both channels provide their
channel numbers as their report word and set the TCINTEN bit to 1 to generate an interrupt after
completion. When channel 3 fills an input buffer, the E3 bit in the interrupt pending register (IPR) is set to
1; when channel 2 empties an output buffer, the E2 bit in IPR is set to 1. The CPU must manually clear
these bits. With the channel parameters set, the CPU polls IPR to determine when to switch. The EDMA3
and CPU could alternatively be configured such that the channel completion interrupts the CPU. By doing
this, the CPU could service a background task while waiting for the EDMA3 to complete.
SPRUG34 – November 2008 EDMA3 Transfer Examples 79
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