2.10.1 DMA/QDMA Channel to Event Queue Mapping
2.10.2 Queue RAM Debug Visibility
2.10.3 Queue Resource Tracking
2.10.4 Performance Considerations
Event Queue(s)
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Each of the 64 DMA channels and 8 QDMA channels are independently programmed to map to a specific
queue using the DMA queue number register (DMAQNUM) and the QDMA queue number register
(QDMANUM). The mapping of DMA/QDMA channels is critical to achieving the desired performance level
for the EDMA and most importantly in meeting real-time deadlines. See
Note:
If an event is ready to be queued and both the event queue and the EDMA3 transfer
controller associated to the event queue are empty, then the event bypasses the event
queue, and goes to the PaRAM processing logic and eventually to the transfer request
submission logic for submission to the EDMA3TC. In this case, the event is not logged in the
event queue status registers.
Each event queue has 16 entries. These 16 entries are managed in a circular FIFO manner. All event
queue entries for all event queues are software readable by the event queue entry register (Q
x
E
x
).
Additionally, for each queue there is a queue status register (QSTAT
n
).
These registers provide user visibility and may be helpful while debugging real-time issues (typically
post-mortem), involving multiple events and event sources. The event queue entry register (Q
x
E
x
)
uniquely identifies the specific event type (event-triggered, manually-triggered, chain-triggered, and QDMA
events) along with the event number (for DMA/QDMA channels) that are in the queue or have been
de-queued (passed through the queue). QSTAT
n
includes fields for the start pointer (STRTPTR) that
provides the offset to the head entry of an event. It also includes a NUMVAL field that provides the total
number of valid entries residing in the event queue at a given instance of time. The STRTPTR field may
be used to index appropriately into the 16 event entries. The NUMVAL number of entries starting from
STRTPTR are indicative of events still queued in the respective queue. The remaining entries may be
read to determine which events have already been de-queued and submitted to the associated transfer
controller.
The EDMA3CC event queue includes watermarking/threshold logic that allows you to keep track of
maximum usage of all event queues. This is useful for debugging real-time deadline violations that may
result from head-of-line blocking on a given EDMA3 event queue.
You can program the maximum number of events that can queue up in an event queue by programming
the threshold value (between 0 to 15) in the queue watermark threshold A register (QWMTHRA). The
maximum queue usage is recorded actively in the watermark (WM) field of the queue status register
(QSTAT
n
) that keeps getting updated based on a comparison of number of valid entries, which is also
visible in the NUMVAL bit in QSTAT
n
and the maximum number of entries (WM bit in QSTAT
n
).
If the queue usage is exceeded, this status is visible in the EDMA3CC registers: the QTHRXCD
n
bit in the
channel controller error register (CCERR) and the THRXCD bit in QSTAT
n
, where
n
stands for the event
queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt.
The main switched central resource (SCR) (see the data manual) arbitrates bus requests from all the
masters (ARM, master peripherals, VPSS, and the EDMA3 transfer controllers (TC0 and TC1)) to the
shared slave resources (peripherals and memories).
The priorities of transfer requests (read and write commands) from the EDMA3 transfer controllers with
respect to other masters within the system are programmed using the queue priority register (QUEPRI).
QUEPRI programs the priority of the event queues (or indirectly, TC0 and TC1, since Queue0 transfer
requests are submitted to TC0 and Queue1 transfer requests are submitted to TC1).
Therefore, the priority of unloading queues has a secondary affect compared to the priority of the transfers
as they are executed by the EDMA3TC (dictated by the priority set using QUEPRI).
EDMA3 Architecture
56
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