Texas Instruments TMS320C6474 Manual Download

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TMS320C6474

www.ti.com

SPRS552F – OCTOBER 2008 – REVISED JULY 2010

Table 7-55. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

02C8 0660

RX0CP

Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register

02C8 0664

RX1CP

Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register

02C8 0668

RX2CP

Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register

02C8 066C

RX3CP

Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register

02C8 0670

RX4CP

Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register

02C8 0674

RX5CP

Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register

02C8 0678

RX6CP

Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register

02C8 067C

RX7CP

Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register

02C8 0680 - 02C8 06FC

Reserved

02C8 0700 - 02C8 077C

Reserved

02C8 0780 - 02C8 0FFF

Reserved

Table 7-56. EMAC Statistics Registers

HEX ADDRESS

ACRONYM

REGISTER NAME

02C8 0200

RXGOODFRAMES

Good Receive Frames Register

02C8 0204

RXBCASTFRAMES

Broadcast Receive Frames Register (Total number of
Good Broadcast Frames Receive)

02C8 0208

RXMCASTFRAMES

Multicast Receive Frames Register (Total number of Good
Multicast Frames Received)

02C8 020C

RXPAUSEFRAMES

Pause Receive Frames Register

02C8 0210

RXCRCERRORS

Receive CRC Errors Register (Total number of Frames
Received with CRC Errors)

02C8 0214

RXALIGNCODEERRORS

Receive Alignment/Code Errors register (Total number of
frames Received with alignment/code errors)

02C8 0218

RXOVERSIZED

Receive Oversized Frames Register (Total number of
Oversized Frames Received)

02C8 021C

RXJABBER

Receive Jabber Frames Register (Total number of Jabber
Frames Received)

02C8 0220

RXUNDERSIZED

Receive Undersized Frames Register (Total number of
Undersized Frames Received)

02C8 0224

RXFRAGMENTS

Receive Frame Fragments Register

02C8 0228

RXFILTERED

Filtered Receive Frames Register

02C8 022C

RXQOSFILTERERED

Received QOS Filtered Frames Register

02C8 0230

RXOCTETS

Receive Octet Frames Register (Total number of
Received Bytes in Good Frames)

02C8 0234

TXGOODFRAMES

Good Transmit Frames Register (Total number of Good
Frames Transmitted)

02C8 0238

TXBCASTFRAMES

Broadcast Transmit Frames Register

02C8 023C

TXMCASTFRAMES

Multicast Transmit Frames Register

02C8 0240

TXPAUSEFRAMES

Pause Transmit Frames Register

02C8 0244

TXDEFERED

Deferred Transmit Frames Register

02C8 0248

TXCOLLISION

Transmit Collision Frames Register

02C8 024C

TXSINGLECOLL

Transmit Single Collision Frames Register

02C8 0250

TXMULTICOLL

Transmit Multiple Collision Frames Register

Peripheral Information and Electrical Specifications

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TMS320C6474

Summary of Contents for TMS320C6474

Page 1: ...non UMTS Systems System PLL and PLL Controller DDR PLL 16 32 Bit DDR2 667 Memory Controller and PLL Controller Dedicated to DDR2 EDMA3 Controller 64 Independent Channels Memory Controller Antenna Interface High Performance Multicore DSP C6474 6 Configurable Links Full Duplex Instruction Cycle Time Supports OBSAI RP3 Protocol v1 0 1 2 GHz Device 0 83 ns 768 Mbps 1 536 3 072 Gbps Link Rates 1 GHz De...

Page 2: ...r mode 0 065 mm 7 Level Cu Metal Process CMOS 16 General Purpose I O GPIO Pins SmartReflex Class 0 0 9 V to 1 2 V Adaptive Internal Semaphore Module Core Voltage Software Method to Control Access to 1 8 V 1 1 V I Os Shared Resources 1 1 CUN GUN ZUN BGA Package Bottom View The devices are designed for a package temperature range of 0 C to 100 C commercial temperature range 1 GHz device 40 C to 100 ...

Page 3: ...2 KB each This memory can be configured as mapped RAM cache or some combination of the two When configured as cache L1 program L1P is a direct mapped cache where as L1 data L1D is a two way set associative cache The level 3 L3 ROM is 64 KB in the device The C64x megamodule also has a 32 bit peripheral configuration CFG port an internal DMA IDMA controller a system component with reset boot control...

Page 4: ...Accelerators The device has two high performance embedded coprocessors enhanced Viterbi Decoder Coprocessor VCP2 and enhanced turbo decoder coprocessor TCP2 that significantly speed up channel decoding operations on chip The VCP2 operating at CPU clock divided by 3 can decode over 694 7 95 Kbps adaptive multi rate AMR K 9 R 1 3 voice channels The VCP2 supports constraint lengths K 5 6 7 8 and 9 ra...

Page 5: ...itched Central Resource SCR DDR2 Memory Controller PLL2 Serial RapidIO 2x TCP2 VCP2 McBSP0 EMAC 10 100 1000 SGMII MDIO Timer 0 5 I2C GPIO16 FSYNC Antenna Interface 32 DDR2 SDRAM L1 Data Memory Controller Memory Protect Bandwidth Mgmt DSP Subsystem 1 DSP Subsystem 0 2 McBSP1 16 D2 M2 xx xx S2 L2 16 32 bit Instruction Dispatch Instruction Decode Control Registers SPLOOP Buffer In Circuit Emulation T...

Page 6: ... 45 7 7 Reset Controller 112 3 3 Device State Control Registers 46 7 8 PLL1 and PLL1 Controller 117 3 4 Device Status Register Descriptions 47 7 9 PLL2 and PLL2 Controller 130 3 5 Inter DSP Interrupt Registers IPCGR0 IPCGR2 7 10 DDR2 Memory Controller 132 and IPCAR0 IPCAR2 49 7 11 I2C Peripheral 135 3 6 JTAG ID JTAGID Register Description 50 7 12 Multichannel Buffered Serial Port McBSP 140 3 7 Deb...

Page 7: ...able updates to the C64x device family specifically relating to the TMS320C6474 device have been incorporated C6474 Revision History SEE ADDITIONS MODIFICATIONS DELETIONS Section 7 3 1 Power Supply Sequencing Added Footnote 1 to Table 7 1 Timing Requirements for Power Supply Ramping Modified Figure 7 4 Power Supply Timing Section 7 7 2 Warm Reset Added last paragraph Copyright 2008 2010 Texas Inst...

Page 8: ...y SYSCLKOUT 1 General Purpose Input Output Port GPIO 16 Decoder Coprocessors VCP2 clock source CPU 3 clock frequency 1 TCP2 clock source CPU 3 clock frequency 1 On Chip Memory Size Bytes 3200 KB Organization 32KB L1P Program Cache SRAM Cache 32KB L1D Data Cache SRAM Cache 32KB Data Memory Controller 3072KB Total L2 Unified Memory SRAM Cache 64KB L3 ROM CPU Megamodule Revision ID Register 0x0 Revis...

Page 9: ...cluding a complex multiply There is also support for Galois filed multiplication for 8 bit and 32 bit data Many communications algorithms such FFTs and modems require complex multiplication The complex multiply CMPY instruction takes four 16 bit inputs and produces a 32 bit real and a 32 bit imaginary output There are also complex multiplies with rounding capability that produces one 32 bit packed...

Page 10: ...tion to sensitive resources Local memory is divided into multiple pages each with read write and execute permissions Time Stamp Counter Primarily targeted for real time operating system RTOS robustness a free running time stamp counter is implemented in the CPU that is not sensitive to system stalls For more details on the C64x CPU and its enhancements over the C64x architecture see the following ...

Page 11: ...2x 1x 32 LSB 32 MSB 32 LSB 32 MSB dst2 B B A 8 8 8 8 32 32 32 32 C C Even register file A A0 A2 A4 A30 Even register file B B0 B2 B4 B30 D D D D TMS320C6474 www ti com SPRS552F OCTOBER 2008 REVISED JULY 2010 A On M unit dst2 is 32 MB B On M unit dst1 is 32 LSB C On 64x CPU M unit src2 is 32 bits on C64x CPU M unit src2 is 64 bits D On L and S units odd dst connects to odd register files and even d...

Page 12: ...hip Interrupt Controller 0 CIC0 0288 0100 0288 01FF 256 Chip Interrupt Controller 1 CIC1 0288 0200 0288 02FF 256 Chip Interrupt Controller 2 CIC2 0288 0300 0288 03FF 256 Chip Interrupt Controller 3 CIC3 0288 0400 0288 0403 4 DSP Trace Formatter 1 DTF1 0288 0404 0288 0407 4 DSP Trace Formatter 2 DTF2 0288 0408 0288 040B 4 DSP Trace Formatter 3 DTF3 0288 040C 0288 07FF 1K 6 Reserved 0288 0800 0288 0...

Page 13: ... 0000 02AD 7FFF 32K Embedded Trace Buffer 0 ETB0 02AD 8000 02AD FFFF 32K Embedded Trace Buffer 1 ETB1 02AE 0000 02AE 7FFF 32K Embedded Trace Buffer 2 ETB2 02AE 8000 02AF FFFF 96K Reserved 02B0 0000 02B0 00FF 256 GPIO 02B0 0100 02B0 1FFF 8K 256 Reserved 02B0 2000 02B0 23FF 1K Reserved 02B0 2400 02B0 3FFF 7K Reserved 02B0 4000 02B0 407F 128 I2C Data and Control 02B0 4080 02B3 FFFF 256K 128 Reserved ...

Page 14: ... 1197 FFFF 512K Reserved 1198 0000 119F FFFF 512K Reserved 11A0 0000 11DF FFFF 4M Reserved 11E0 0000 11E0 7FFF 32K C64x Megamodule Core 1 L1P SRAM 11E0 8000 11EF FFFF 1M 32K Reserved 11F0 0000 11F0 7FFF 32K C64x Megamodule Core 1 L1D SRAM 11F0 8000 11FF FFFF 1M 32K Reserved 1200 0000 127F FFFF 8M Reserved 1280 0000 1287 FFFF 512K C64x Megamodule Core 2 L2 SRAM 1288 0000 128F FFFF 512K 1290 0000 12...

Page 15: ...ot Modes Supported The device supports several boot processes which leverage the internal boot ROM Most boot processes are software driven using the BOOTMODE 3 0 device configuration inputs to determine the software configuration that must be completed From a hardware perspective there are three possible boot modes No Boot BOOTMODE 3 0 0000b With no boot the CPU executes directly from the internal...

Page 16: ...rings the other C64x Megamodule Cores out of reset Reserved 0111b Reserved Serial RapidIO Boot Config 0 1000b The C64x Megamodule Core 0 configures the SRIO and an external host loads the application via SRIO peripheral using directIO protocol A doorbell interrupt is used to Serial RapidIO Boot Config 1 1001b indicate that the code has been loaded For more details on the Serial RapidIO Serial Rapi...

Page 17: ...18 VSS GP15 TRTCLK DVDD18 GP12 GP11 VSS GP13 VSS VSS GP14 GP10 DVDD18 VSS VSS GP08 GP07 DVDD18 CVDD VSS CVDD VSS CVDD VSS FSYNC CLKN FRAME BURSTP VSS DVDD18 TMS GP02 TRST TDO TCK DVDD18 GP05 GP06 TDI VSS VSS CVDD VSS CVDD VSS CVDD EMU10 DVDD18 EMU15 VSS GP03 GP01 DVDD18 DVDD18 GP04 EMU00 VSS EMU01 EMU07 EMU11 GP00 GP09 CVDD VSS CVDD VSS CVDD VSS VSS CVDD VSS CVDD VSS CVDD CVDD VSS CVDD VSS CVDD VS...

Page 18: ...VSS AIF_VDDT11 AIF_VDDA11 DDRRCV ENIN0 DVDD18 VSS DDRRCV ENOUT0 VSS DVDD18 DDRD05 DDRD06 DDRD04 DDRD02 VSS DDRDQS0P DDRDQS0N DVDD18 DVDD18 DDRDQM0 DDRD01 DDRD03 DDRD00 AIFTXN1 VSS AIF_VDDA11 VSS AIF_VDDD11 VSS VSS AIF_VDDD11 VSS AIF_VDDD11 AIF_VDDD11 VSS AIF_VDDD11 VSS VSS DDRCLK OUTN0 DDRCLK OUTP0 DVDD18 VSS CVDD CVDD VSS VSS AIF_VDDD11 VSS CVDD CVDD CVDD VSS VSS VSS CVDD CVDD VSS DDRD07 DVDD18 V...

Page 19: ... DDRRCV ENOUT1 VSS DVDD18 VSS VSS VSS VSS VSS SGR_VDDA11 DX0 MDIO VSS RSV18 MDCLK VSS SGR_VDDT11 SGMIIRXN SGMIIRXP DDRDQM3 VSS DDRD19 DDRD17 DDRD21 DDRD22 RSV26 VSS DDRDQS2N DDRDQS2P DDRD23 VSS DDRDQM2 DDRD16 DDRD18 DDRD20 DDRA08 CVDD SGR_VDDD11 VSS CVDD VSS VSS CVDD VSS CVDD VSS CVDD CVDD VSS CVDD VSS A 26 25 24 23 22 21 20 19 18 17 16 15 27 A SGMIITXP DVDD18 SGR_VDDR18 SGMIITXN VSS DVDD18 CLKR1 ...

Page 20: ...VDD18 NMI2 NMI1 RSV29 NMI0 EMU05 EMU04 EMU18 EMU08 VSS DVDD18 DVDD18 VSS EMU12 EMU17 A 12 11 10 9 8 7 6 5 4 3 2 1 13 A DVDD18 DVDD18 VSS VSS VSS RIORXN0 RIORXP0 VSS RIORXP1 RIORXN1 RSV19 RSV15 VSS SGR_VDDT11 RSV16 VSS VSS VSS RSV20 VSS VSS VSS 14 M L K N P J VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS VSS CVDD VSS SGR_VDDD11 SGR_VDDD11 VSS CVDD VSS VSS CVDD VSS CVDD VSS CVDD CVDD VSS CVDD VSS...

Page 21: ... Controller Clock PLL2 TDO TDI TCK TRST EMU00 EMU01 EMU02 EMU14 EMU15 EMU16 EMU17 EMU18 RESET NMI0 NMI1 NMI2 XWRST AVDD118 TMS320C6474 www ti com SPRS552F OCTOBER 2008 REVISED JULY 2010 2 6 Signal Groups Description Figure 2 6 CPU and Peripheral Signals Copyright 2008 2010 Texas Instruments Incorporated Device Overview 21 Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 22: ...ENOUT 2 0 DDRODT DDRSLRATE VREFSSTL DDRBA0 DDRBA1 DDRBA2 External Memory Controller Bank Address DDR Memory Controller 32 bit Data Bus 32 TMS320C6474 SPRS552F OCTOBER 2008 REVISED JULY 2010 www ti com Figure 2 7 DDR Memory Controller Peripheral Signals 22 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 23: ...P12 GP13 GP14 GP15 GPIO General Purpose Input Output 0 GPIO Port TIMO1 TIMI1 Timer Pin Manager Timers 64 Bit TMS320C6474 www ti com SPRS552F OCTOBER 2008 REVISED JULY 2010 A Reference Clock to drive RapidIO and SGMII Figure 2 8 Timers GPIO RapidIO Peripheral Signals Copyright 2008 2010 Texas Instruments Incorporated Device Overview 23 Submit Documentation Feedback Product Folder Link s TMS320C6474...

Page 24: ...N FSYNCCLKP ALTFSYNCCLK TRTCLK SMFRAMECLK FSYNC Clock Frame Synchroniztion FSYNC AIFTXN 5 0 AIFTXP 5 0 AIFRXN 5 0 AIFRXP 5 0 SCL SDA Transmit SCL Receive Antenna Interface AIF I2C TMS320C6474 SPRS552F OCTOBER 2008 REVISED JULY 2010 www ti com Figure 2 9 McBSP FSYNC AIF I2C Peripheral Signals 24 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product...

Page 25: ...IO Ethernet MAC EMAC and MDIO MDIO MDCLK TMS320C6474 www ti com SPRS552F OCTOBER 2008 REVISED JULY 2010 A Reference Clock to drive RapidIO and SGMII Figure 2 10 EMAC MDIO SGMII Peripheral Signals Copyright 2008 2010 Texas Instruments Incorporated Device Overview 25 Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 26: ...s are mapped to C64x Megamodule Core 0 C64x Megamodule Core 1 and C64x Megamodule Core NMI1 J2 I IPD 2 respectively NMIs are edge driven rising edge Any noise on the NMI pin NMI2 J1 I IPD may trigger an NMI interrupt therefore if the NMI pin is not used it is recommended that the NMI pin be grounded rather than relying on the IPD XWRST AD5 I Warm Reset RESETSTAT AF4 O Reset Status Output POR AE5 I...

Page 27: ...M2 B24 O Z DDRDQM3 H24 O Z DDRCE L24 O Z DDR2 EMIF Chip Enable DDRBA0 T25 O Z DDRBA1 R25 O Z DDR Bank Address DDRBA2 U25 O Z DDRA00 K25 O Z DDRA01 N25 O Z DDRA02 M25 O Z DDRA03 R26 O Z DDRA04 L25 O Z DDRA05 N27 O Z DDRA06 L26 O Z DDR2 EMIF Address Bus DDRA07 U26 O Z DDRA08 K26 O Z DDRA09 R27 O Z DDRA10 P25 O Z DDRA11 L27 O Z DDRA12 U27 O Z DDRA13 K27 O Z DDRCLKOUTP0 V25 O Z DDRCLKOUTN0 V24 O Z DDR...

Page 28: ...26 I O Z DDRD19 D24 I O Z DDRD20 B27 I O Z DDRD21 D26 I O Z DDRD22 D27 I O Z DDRD23 C27 I O Z DDRD24 F24 I O Z DDRD25 F25 I O Z DDRD26 F26 I O Z DDRD27 F27 I O Z DDRD28 G27 I O Z DDRD29 H25 I O Z DDRD30 H26 I O Z DDRD31 H27 I O Z DDRCAS N26 O Z DDR2 EMIF Column Address Strobe DDRRAS M24 O Z DDR2 Row Address Strobe DDRWE P24 O Z DDR2 EMIF Write Enable DDRCKE T24 O Z DDR2 EMIF Clock Enable DDRDQS0P ...

Page 29: ... I O Z IPU EMU02 N3 I O Z IPU EMU03 N1 I O Z IPU EMU04 M2 I O Z IPU EMU05 M1 I O Z IPU EMU06 N4 I O Z IPU EMU07 R3 I O Z IPU EMU08 M4 I O Z IPU EMU09 N2 I O Z IPU Emulation and Trace Port EMU10 R1 I O Z IPU EMU11 T2 I O Z IPU EMU12 L3 I O Z IPU EMU13 P4 I O Z IPU EMU14 K2 I O Z IPU EMU15 T1 I O Z IPU EMU16 P3 I O Z IPU EMU17 L4 I O Z IPU EMU18 M3 I O Z IPU FRAME SYNCHRONIZATION FSYNC FSYNCCLKN AD8...

Page 30: ...Data open drain MULTICHANNEL BUFFERED SERIAL PORT McBSP CLKS0 D20 I IPD McBSP0 Module Clock CLKR0 B20 I O Z IPD McBSP0 Receive Clock CLKX0 C20 I O Z IPD McBSP0 Transmit Clock DR0 A20 I IPD McBSP0 Receive Data DX0 D19 O Z IPD McBSP0 Transmit Data FSR0 B21 I O Z IPD McBSP0 Receive Frame Sync FSX0 A21 I O Z IPD McBSP0 Transmit Frame Sync CLKS1 A25 I IPD McBSP1 Module Clock CLKR1 A24 I O Z IPD McBSP1 ...

Page 31: ...connected RSV06 AE7 O Reserved unconnected RSV07 AE8 O Reserved unconnected RSV08 AF24 O Reserved unconnected RSV09 AF25 O Reserved unconnected RSV10 K4 I O Z IPU Reserved unconnected RSV11 K3 I O Z IPU Reserved unconnected RSV12 K1 I O Z IPU Reserved unconnected RSV13 G4 O Z IPD Reserved unconnected RSV14 F3 O Z IPD Reserved unconnected RSV15 D7 A Reserved GND connection RSV16 C7 A Reserved uncon...

Page 32: ...OLTAGE PINS J11 S J17 S J19 S J9 S K10 S K18 S L11 S L13 S L15 S L17 S L19 S L9 S M10 S M12 S M14 S M16 S M18 S N11 S CVDD N13 S 0 9 1 2 V Core Supply Voltage N15 S N17 S N19 S N9 S P10 S P12 S P14 S P16 S P18 S R11 S R13 S R15 S R17 S R19 S R9 S T10 S T12 S T14 S 32 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 33: ...1 V SRIO SGMII Serdes Analog Supply E11 A E15 A AVDD218 AG23 A 1 8 V PLL Supply AVDD118 AG9 A AG26 S U17 S V16 S AIF _V DDD11 V18 S 1 1 V AIF Serdes Digital Supply W15 S W17 S W19 S J13 S J15 S SGR_V DDD11 K12 S 1 1 V SRIO SGMII Serdes Digital Supply K14 S K16 S CVDDMON AG6 S 0 9 1 2 V CVDD Supply Monitor AD19 S AIF_VDDR18 1 8 V AIF Serdes Regulator Supply AD15 S C12 S SGR_VDDR18 1 8 V SRIO SGMII ...

Page 34: ... S AA23 S AA5 S AB26 S AC1 S AC23 S AC5 S AC7 S AC9 S AF5 S AG1 S AG27 S AG8 S E1 S E19 S E21 S E23 S DVDD18 E27 S 1 8 V I O Supply E5 S G23 S G5 S H2 S J23 S J27 S J5 S L1 S L23 S L5 S M26 S N23 S N5 S P2 S P26 S R23 S R5 S U1 S U23 S U5 S V26 S 34 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 35: ...O Supply Y2 S Y24 S DVDD18MON AG7 S 1 8 V DVDD18 Supply Monitor AC11 S AC14 S AC17 S AIF_VDDT11 AC20 S 1 1 V AIF Serdes Termination Supply AF15 S AF19 S AG11 S B13 S B17 S B8 S SGR_VDDT11 1 1 V SRIO SGMII Serdes Termination Supply E13 S E17 S E9 S Copyright 2008 2010 Texas Instruments Incorporated Device Overview 35 Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 36: ... NO GROUND PINS A11 A14 A17 A2 A26 A3 A4 A6 A7 A8 AA1 AB1 AB23 AB27 AB5 AC10 AC13 AC16 AC19 AC2 AC22 VSS AC6 GND Ground AC8 AD1 AD11 AD18 AD2 AD22 AE1 AE11 AE12 AE15 AE16 AE2 AE20 AE3 AF1 AF11 AF14 AF18 AF2 AF20 AF23 36 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 37: ... DESCRIPTION NAME NO AF26 AF27 AF3 AF8 AG12 AG15 AG16 AG19 AG2 AG22 AG3 AG4 AG5 B1 B10 B11 B14 B15 B16 B2 B23 VSS B3 GND Ground B4 B5 B6 B7 B9 C1 C15 C18 C2 C24 C3 C8 D1 D10 D11 D13 D14 D15 D16 D17 D2 Copyright 2008 2010 Texas Instruments Incorporated Device Overview 37 Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 38: ...AL DESCRIPTION NAME NO D23 D3 D8 E10 E12 E14 E16 E18 E2 E20 E22 E26 E8 F1 F23 F5 G1 G24 H1 H23 H5 VSS J10 GND Ground J12 J14 J16 J18 J26 K11 K13 K15 K17 K19 K23 K5 K9 L10 L12 L14 L16 L18 L2 M11 M13 38 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 39: ... DESCRIPTION NAME NO M15 M17 M19 M23 M27 M5 M9 N10 N12 N14 N16 N18 P1 P11 P13 P15 P17 P19 P23 P27 P5 VSS P9 GND Ground R10 R12 R14 R16 R18 R24 T11 T13 T15 T17 T19 T23 T27 T5 T9 U10 U12 U14 U16 U18 U2 Copyright 2008 2010 Texas Instruments Incorporated Device Overview 39 Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 40: ...nctions continued SIGNAL TYPE 1 IPD IPU 2 SIGNAL DESCRIPTION NAME NO U24 V11 V13 V15 V17 V19 V23 V27 V5 VSS GND Ground V9 W10 W12 W14 W16 W18 Y1 Y23 Y5 40 Device Overview Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 41: ...20C6474ZUN Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device ...

Page 42: ... processor Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com SPRU732 TMS320C64x C64x DSP CPU and Instruction Set Reference Guide Describes the CPU architecture pipeline instruction set and interrupts for the TMS320C64x and TMS320C64x digital signal processors DSPs of the TMS320C6000 DSP family The C64x C64...

Page 43: ...ered serial port McBSP in the digital signal processors DSPs of the TMS320C6474 device SPRUG18 TMS320C6474 DSP 64 Bit Timer User s Guide This document provides an overview of the 64 bit timer in the TMS320C6474 digital signal processors DSPs SPRUG19 TMS320C6474 DSP DDR2 Memory Controller User s Guide This document describes the DDR2 memory controller in the TMS320C6474 digital signal processors DS...

Page 44: ...zer deserializer SERDES based interfaces on the TMS320C6474 DSP SPRAAX3 TMS320C6474 Power Consumption Summary This document discusses the power consumption of the Texas Instruments TMS320C6474 digital signal processor DSP SPRAB25 How to Approach Inter Core Communication on TMS320C6474 This document discusses the of handling the three cores that are present on the TMS320C6474 DSP along with what fe...

Page 45: ...or Table 3 1 Device Configuration Pins CONFIGURATION DEFAULT IPU IPD FUNCTIONAL DESCRIPTION PIN BOOTMODE 3 0 0000b Boot Mode Selection LENDIAN 1b Device Endian Mode 0 Big Endian 1 Little Endian DEVNUM 3 0 0000b Device number CORECLKSEL 0b Core Clock Select 0 SYSCLK is shared between the Antenna Interface and the input to PLLCTL1 1 ALTCORECLK is used as the input to PLLCTL1 and SYSCLK is used only ...

Page 46: ... 0830 0288 0833 4B Reserved 0288 0834 0288 083B 8B EFUSE_MAC Required for EMAC boot 0288 083C 0288 083F 4B PRI_ALLOC Priority Allocation Register 0288 0840 0288 08FF 192B Reserved N A 0288 0900 0288 0903 4B IPCGR0 Register provided to facilitate inter DSP interrupts and utilized by hosts or C64x Megamodules to generate interrupts to other DSPs 0288 0904 0288 0907 4B IPCGR1 Register provided to fac...

Page 47: ...egister is reset on all hard resets and is locked after the first write 31 3 2 1 0 Reserved CLKS1 CLKS0 SYSCLKOUTEN R 00000000000000000000000000000 R W 0 R W 0 R W 1 LEGEND R W Read Write R Read only n value after reset Figure 3 1 Device Configuration Register DEVCFG Table 3 3 Device Configuration Register DEVCFG Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 CLKS1 McBSP1 ...

Page 48: ...bootmode see Section 2 4 0000 No Boot 0001 I2C Master Boot Slave Address 0x50 0010 I2C Master Boot Slave Address 0x51 0011 I2C Slave Boot 0100 EMAC Master Boot 0101 EMAC Slave Boot 0110 EMAC Forced Mode Boot 0111 Reserved 1000 RapidIO Boot Configuration 0 1001 RapidIO Boot Configuration 1 1010 RapidIO Boot Configuration 2 1011 RapidIO Boot Configuration 3 11xx Reserved 1 Reserved Reserved 0 LENDIA...

Page 49: ... R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 SRCS11 SRCS10 SRCS9 SRCS8 SRCS7 SRCS6 SRCS5 SRCS4 SRCS3 SRCS2 SRCS1 SRCS0 Reserved IPCG R W R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 000 R W 0 0 LEGEND R W Read Write R Read only n value after reset Figure 3 3 IPC Generation Registers IPCGR0 IPCGR2 Tab...

Page 50: ...814 For the actual register bit names and their associated bit field descriptions see Figure 3 5 and Table 3 7 31 28 27 12 11 1 0 VARIANT PART NUMBER MANUFACTURER LSB 4 bit 16 bit 11 bit R n R 0000 0000 1001 0010b R 000 0001 0111b R 1 LEGEND R Read only n value after reset Figure 3 5 JTAG ID JTAGID Register Table 3 7 JTAG ID JTAGID Register Field Descriptions Bit Field Value Description 31 28 VARI...

Page 51: ...ch fabrics through which masters and slaves communicate The data switch fabric known as the data switched central resource SCR is a high throughput interconnect mainly used to move data across the system for more information see Section 4 3 The SCR adds no latency and allows seamless arbitration i e no dead cycles inserted by the fabric between the masters and slaves The data SCR connects masters ...

Page 52: ...es and masters through the data switched central resource SCR Masters are shown on the right and slaves on the left The number of master ports for the EDMA is 2x the number of TPTCs implemented because each TPTC has a read port and a write port 52 System Interconnect Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 53: ...C64x Megamodule Core 2 C64x Megamodule Core 3 Bridge 4 Bridge 3 Bridge 2 SCR B 64 bit VBUSM Transfer Controller TC 3 channels SCR A 128 bit VBUSM Bridge 22 Bridge 23 Bridge 24 AIF Read AIF Write C64x Megamodule Core 1 C64x Megamodule Core 2 C64x Megamodule Core 3 Bridge 9 SCRC 32 bit VBUSP ROM DDR2 EMIF MCBSPs 2 Bridge 28 Bridge 12 Bridge 11 Bridge 29 Bridge 10 SCRD CFG VCP TCP TMS320C6474 www ti ...

Page 54: ...2 N N Y Y Y Y SCR B Br3 N N Y Y Y Y TPTC3 RM Y N Y Y Y Y TPTC3 WM Y N Y Y Y Y TPTC4 RM N Y Y Y Y Y TPTC4 WM N Y Y Y Y Y TPTC5 RM N Y Y Y Y Y TPTC5 WM N Y Y Y Y Y SCR B is a secondary 64 bit switch fabric primarily dedicated to slave peripherals that require servicing by the TPDMA Additionally master peripherals that are sub 128 bit are connected to this switch fabric There are two master ports on ...

Page 55: ...Br5 N N Y Y Y Y N N C64x Megamodule Core 0 Y Y N Y Y Y N Y C64x Megamodule Core 1 Y Y N Y Y Y N Y C64x Megamodule Core 2 Y Y N Y Y Y N Y The SCR C connection matrix allows for the master to SCR B to access any of the 32 bit slaves on the switch fabric plus the boot ROM The SCR C switch connections between SCR B Br9 to McBSP0 and McBSP1 are required 4 3 Configuration Switch Fabric Figure 4 2 shows ...

Page 56: ...idge 13 SCR E 32 bit VBUSP TPTCs 6 E D M A 3 TPCC Bridge 20 ETB 3 Semaphore FSYNC CFGC CIC DTF GPIO S McBSPs 2 I2C GPSC PLL Ctrls 2 TPMGR Timer64s 6 T i m e r MDIO CP GMAC Ethernet CPPI SGMII Wrapper EMIC E M A C S Reserved TMS320C6474 SPRS552F OCTOBER 2008 REVISED JULY 2010 www ti com Figure 4 2 Configuration Switched Central Resource Block Diagram 56 System Interconnect Copyright 2008 2010 Texas...

Page 57: ...ltiple masters try to access the configuration SCR Priority is also enforced on the configuration SCR side when a master through the data SCR tries to access the same endpoint as the C64x Megamodule The 4 Byte PRI_ALLOC register address range is 0288 083C 0288 083F 31 6 5 3 2 0 Reserved RapidIO CPPI EMAC RW 00 0000 0000 0000 0000 0000 0000 RW 001 RW 001 Figure 4 3 Priority Allocation Register PRI_...

Page 58: ...474 SPRS552F OCTOBER 2008 REVISED JULY 2010 www ti com 5 C64x Megamodule 5 1 Megamodule Diagram The C64x Megamodule consists of several components the C64x CPU and associated C64x Megamodule core level one and level two memories L1P L1D L2 data trace formatter DTF embedded trace buffer ETB the interrupt controller power down controller external memory controller and a dedicated power sleep control...

Page 59: ...is 32K bytes with no wait states After core reset L1P and L1D cache are configured as all cache by default The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register L1PMODE and the L1DMODE field of the L1D Configuration Register L1DCFG of the C64x Megamodule L1D is a two way set associative cache while L1P is a direct mapped cache L1P and L1...

Page 60: ...e following figure provides the possible memory maps for the local L2 The L2 memory is typically shared across the two unified memory access ports UMAP0 and UMAP1 The L2 SRAM begins at the same address Figure 5 4 L2 Memory Configuration 1024KB All memory on the device has a unique location in the memory see Section 2 3 Memory Map Summary Global addresses that are accessible to all masters in the s...

Page 61: ...0x0088 0000 0x008F FFFF 32 KB 32 KB 32 KB 0x0090 0000 0x0097 FFFF N A N A N A 0x0098 0000 0x009F FFFF N A N A N A Table 5 2 shows the memory addresses used to access the L2 memory Cells in normal font should be used by the software for memory accesses The L2 addresses are common between all three cores allowing for the same code to be run unmodified on each Cells in italic N A are not accessible M...

Page 62: ...ccess type are stored Signal event to CPU interrupt controller The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller 5 4 Bandwidth Management When multiple requesters contend for a single C64x Megamodule resource the conflict is solved by granting access to the highest priority requestor The following four resources...

Page 63: ...ms for lower overall system power requirements Note that the device does not support power down modes for the L2 memory at this time 5 6 Megamodule Resets Table 5 6 shows the reset types supported on the device and if the resetting affects the Megamodule globally or just locally Table 5 6 Megamodule Reset Global or Local RESET TYPE GLOBAL RESET LOCAL RESET Power On Y Y Warm Y Y System Y Y CPU N Y ...

Page 64: ...egister 0 Events 31 0 0180 0024 EVTSET1 Event Set Register 1 0180 0028 EVTSET2 Event Set Register 2 0180 002C EVTSET3 Event Set Register 3 0180 0030 0180 003C Reserved 0180 0040 EVTCLR0 Event Clear Register 0 Events 31 0 0180 0044 EVTCLR1 Event Clear Register 1 0180 0048 EVTCLR2 Event Clear Register 2 0180 004C EVTCLR3 Event Clear Register 3 0180 0050 0180 007C Reserved 0180 0080 EVTMASK0 Event Ma...

Page 65: ...reset and start executing their codes Table 5 9 Megamodule Power Down Control Registers HEX ADDRESS ACRONYM REGISTER NAME 0181 0000 PDCCMD Power Down Controller Command Register 0181 0004 0181 1FFF Reserved Table 5 10 Megamodule Revision Register HEX ADDRESS ACRONYM REGISTER NAME 0181 2000 MM_REVID Megamodule Revision ID Register 0181 2004 0181 2FFF Reserved Table 5 11 Megamodule IDMA Registers HE...

Page 66: ...ase Address Register for Block Writebacks 0184 4044 L1DWWC L1D Writeback Word Count Register 0184 4048 L1DIBAR L1D Invalidate Base Address Register 0184 404C L1DIWC L1D Invalidate Word Count Register 0184 4050 0184 4FFF Reserved 0184 5000 L2WB L2 Global Writeback Register 0184 5004 L2WBINV L2 Global Writeback and Invalidate Register 0184 5008 L2INV L2 Global Invalidate Register 0184 500C 0184 5024...

Page 67: ... 0184 825C MAR151 Controls DDR2 CE0 Range 9700 0000 97FF FFFF 0184 8260 MAR152 Controls DDR2 CE0 Range 9800 0000 98FF FFFF 0184 8264 MAR153 Controls DDR2 CE0 Range 9900 0000 99FF FFFF 0184 8268 MAR154 Controls DDR2 CE0 Range 9A00 0000 9AFF FFFF 0184 826C MAR155 Controls DDR2 CE0 Range 9B00 0000 9BFF FFFF 0184 8270 MAR156 Controls DDR2 CE0 Range 9C00 0000 9CFF FFFF 0184 8274 MAR157 Controls DDR2 CE...

Page 68: ...gister 11 0184 A230 L2MPPA12 L2 Memory Protection Page Attribute Register 12 0184 A234 L2MPPA13 L2 Memory Protection Page Attribute Register 13 0184 A238 L2MPPA14 L2 Memory Protection Page Attribute Register 14 0184 A23C L2MPPA15 L2 Memory Protection Page Attribute Register 15 0184 A240 L2MPPA16 L2 Memory Protection Page Attribute Register 16 0184 A244 L2MPPA17 L2 Memory Protection Page Attribute ...

Page 69: ...ge Attribute Register 56 0184 A2E4 L2MPPA57 L2 Memory Protection Page Attribute Register 57 0184 A2E8 L2MPPA58 L2 Memory Protection Page Attribute Register 58 0184 A2EC L2MPPA59 L2 Memory Protection Page Attribute Register 59 0184 A2F0 L2MPPA60 L2 Memory Protection Page Attribute Register 60 0184 A2F4 L2MPPA61 L2 Memory Protection Page Attribute Register 61 0184 A2F8 L2MPPA62 L2 Memory Protection ...

Page 70: ...ts 127 96 0184 AD10 L1DMPLKCMD L1D Memory Protection Lock Key Command Register 0184 AD14 L1DMPLKSTAT L1D Memory Protection Lock Key Status Register 0184 AD18 0184 ADFF Reserved 0184 AE00 0184 AE3C 3 Reserved 0184 AE40 L1DMPPA16 L1D Memory Protection Page Attribute Register 16 0184 AE44 L1DMPPA17 L1D Memory Protection Page Attribute Register 17 0184 AE48 L1DMPPA18 L1D Memory Protection Page Attribu...

Page 71: ...UARBU L2D CPU Arbitration Control Register 0184 1004 L2DIDMAARBU L2D IDMA Arbitration Control Register 0184 1008 L2DSDMAARBU L2D Slave DMA Arbitration Control Register 0184 100C L2DUCARBU L2D User Coherence Arbitration Control Register 0184 1010 0184 103F Reserved 0184 1040 L1DCPUARBD L1D CPU Arbitration Control Register 0184 1044 L1DIDMAARBD L1D IDMA Arbitration Control Register 0184 1048 L1DSDMA...

Page 72: ... 1 8 V Single Ended I Os 0 3 V to DVDD18 0 3 V DDR2 0 3 V to 2 45 V Output voltage VO range I2C VCNTL 0 3 V to 2 45 V SERDES 0 3 V to DVDD11 0 3 V 850 MHz and 1 GHz device commercial temperature 0 C to 100 C 4 1 2 GHz device commercial temperature 0 C to 95 C 4 Operating case temperature range TC 1 GHz device extended temperature 40 C to 100 C 4 1 2 GHz device extended temperature 5 40 C to 95 C 4...

Page 73: ...D Peak to peak differential input voltage 250 2000 mV 1 8 V Single 0 65 DVDD18 V Ended I Os VIH High level input voltage 3 I2C VCNTL 0 7 DVDD18 V SmartReflex DDR2 EMIF VREFSSTL 0 125 DVDD18 0 3 V 1 8 V Single 0 35 DVDD18 V Ended I Os VIL Low level input voltage 3 DDR2 EMIF 0 3 VREFSSTL 0 1 V I2C VCNTL 0 3 DVDD18 V 1 2 GHz device commercial 0 95 temperature 1 2 GHz device extended 40 95 temperature...

Page 74: ...X1 DX1 FSR1 IOH output current mA FSX1 DC RESETSTAT SMFRAMECLK MDIO 4 MDCLK DDR2 4 EMU 18 00 8 GPIO 15 0 TIM 1 0 SYSCLKOUT TDO CLKR0 CLKX0 DX0 FSR0 FSX0 CLKR1 6 Low level output CLKX1 DX1 FSR1 IOL mA current DC FSX1 RESETSTAT SMFRAMECLK MDIO 4 MDCLK DDR2 4 Off state output 1 8 V Single Ended IOZ 3 20 20 mA current DC I Os 1 For test conditions shown as MIN MAX or TYP use the appropriate value spec...

Page 75: ...r s guides and design guides A transmission line delay of 2 ns was used for all output measurements except the DDR2 which was evaluated using a 528 ps delay B This figure represents all outputs except differential or I2C Figure 7 1 Test Load Circuit for AC Timing Measurements The load capacitance value stated is for characterization and measurement of AC timing signals This load capacitance value ...

Page 76: ...pplication report literature number SPRAAW7 7 3 2 Power Supply Decoupling In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP These caps need to be close to the DSP no more than 1 25 cm maximum distance to be effective Physically smaller caps are better such as 0402 but need to be evaluated from a yield manufacturing point of...

Page 77: ...ough the power down controller based on its own execution thread or in response to an external stimulus from a host or global controller More information on the power down features of the C64x Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 Table 7 2 lists the Power Sleep Controller PSC registers Table 7 2 Power Sleep Controller Registers HEX ADDRESS ...

Page 78: ...tic power consumption is mainly determined by transistor type and process technology Higher clock rates also increase dynamic power the power used when transistors switch The dynamic power depends mainly on a specific usage scenario clock rates and I O activity Texas Instruments SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device perfor...

Page 79: ...1 14 Timer64_1 0x02920000 0x00010701 0x00010701 0x00010701 15 Timer64_2 0x02930000 0x00010701 0x00010701 0x00010701 16 Timer64_3 0x02940000 0x00010701 0x00010701 0x00010701 17 Timer64_4 0x02950000 0x00010701 0x00010701 0x00010701 18 Timer64_5 0x02960000 0x00010701 0x00010701 0x00010701 19 PLL CTRL 0x029A0000 0x0001080d 0x0001080d 0x0001080d 20 PSC 0x02AC0000 0x44821105 0x44821105 0x44821105 21 GPI...

Page 80: ...titive continuous transfers all with no CPU intervention Chaining allows multiple transfers to execute with one event 256 PaRAM entries Used to define transfer context for channels Each PaRAM entry can be used as a DMA entry QDMA entry or link entry 64 DMA channels Manually triggered CPU writes to channel controller register external event triggered and chain triggered completion of one transfer t...

Page 81: ...EVT4 CIC_EVT_o 4 from Chip Interrupt Controller 11 CIC3_EVT5 CIC_EVT_o 5 from Chip Interrupt Controller 12 XEVT0 McBSP 0 Transmit Event 13 REVT0 McBSP 0 Receive Event 14 XEVT1 McBSP 1 Transmit Event 15 REVT1 McBSP 1Receive Event 16 FSEVT4 Frame Synchronization Event 4 17 FSEVT5 Frame Synchronization Event 5 18 FSEVT6 Frame Synchronization Event 6 19 FSEVT7 Frame Synchronization Event 7 20 FSEVT8 F...

Page 82: ...ent 9 58 GPINT10 GPIO Event 10 59 GPINT11 GPIO Event 11 60 GPINT12 GPIO Event 12 61 GPINT13 GPIO Event 13 62 GPINT14 GPIO Event 14 63 GPINT15 GPIO Event 15 7 5 2 EDMA3 Peripheral Register Description s Table 7 5 EDMA3 Registers HEX ADDRESS ACRONYM REGISTER NAME 02A0 0000 PID Peripheral ID Register 02A0 0004 CCCFG EDMA3CC Configuration Register 02A0 0008 02A0 00FC Reserved 02A0 0100 DCHMAP0 DMA Cha...

Page 83: ...ister 02A0 018C DCHMAP35 DMA Channel 35 Mapping Register 02A0 0190 DCHMAP36 DMA Channel 36 Mapping Register 02A0 0194 DCHMAP37 DMA Channel 37 Mapping Register 02A0 0198 DCHMAP38 DMA Channel 38 Mapping Register 02A0 019C DCHMAP39 DMA Channel 39 Mapping Register 02A0 01A0 DCHMAP40 DMA Channel 40 Mapping Register 02A0 01A4 DCHMAP41 DMA Channel 41 Mapping Register 02A0 01A8 DCHMAP42 DMA Channel 42 Map...

Page 84: ...0280 QUETCMAP Queue to TC Mapping Register 02A0 0284 QUEPRI Queue Priority Register 02A0 0288 02A0 02FC Reserved 02A0 0300 EMR Event Missed Register 02A0 0304 EMRH Event Missed Register High 02A0 0308 EMCR Event Missed Clear Register 02A0 030C EMCRH Event Missed Clear Register High 02A0 0310 QEMR QDMA Event Missed Register 02A0 0314 QEMCR QDMA Event Missed Clear Register 02A0 0318 CCERR EDMA3CC Er...

Page 85: ...6 Event Queue 0 Entry Register 6 02A0 041C Q0E7 Event Queue 0 Entry Register 7 02A0 0420 Q0E8 Event Queue 0 Entry Register 8 02A0 0424 Q0E9 Event Queue 0 Entry Register 9 02A0 0428 Q0E10 Event Queue 0 Entry Register 10 02A0 042C Q0E11 Event Queue 0 Entry Register 11 02A0 0430 Q0E12 Event Queue 0 Entry Register 12 02A0 0434 Q0E13 Event Queue 0 Entry Register 13 02A0 0438 Q0E14 Event Queue 0 Entry R...

Page 86: ...ster 7 02A0 04E0 Q3E8 Event Queue 3 Entry Register 8 02A0 04E4 Q3E9 Event Queue 3 Entry Register 9 02A0 04E8 Q3E10 Event Queue 3 Entry Register 10 02A0 04EC Q3E11 Event Queue 3 Entry Register 11 02A0 04F0 Q3E12 Event Queue 3 Entry Register 12 02A0 04F4 Q3E13 Event Queue 3 Entry Register 13 02A0 04F8 Q3E14 Event Queue 3 Entry Register 14 02A0 04FC Q3E15 Event Queue 3 Entry Register 15 02A0 0500 Q4E...

Page 87: ...18 02A0 061C Reserved 02A0 0620 QWMTHRA Queue Watermark Threshold A Register 02A0 0624 QWMTHRB Queue Watermark Threshold B Register 02A0 0628 02A0 063C Reserved 02A0 0640 CCSTAT EDMA3CC Status Register 02A0 0644 02A0 06FC Reserved 02A0 0700 02A0 07FC Reserved 02A0 0800 MPFAR Memory Protection Fault Address Register 02A0 0804 MPFSR Memory Protection Fault Status Register 02A0 0808 MPFCR Memory Prot...

Page 88: ...errupt Pending High Register 02A0 1070 ICR Interrupt Clear Register 02A0 1074 ICRH Interrupt Clear High Register 02A0 1078 IEVAL Interrupt Evaluate Register 02A0 107C Reserved 02A0 1080 QER QDMA Event Register 02A0 1084 QEER QDMA Event Enable Register 02A0 1088 QEECR QDMA Event Enable Clear Register 02A0 108C QEESR QDMA Event Enable Set Register 02A0 1090 QSER QDMA Secondary Event Register 02A0 10...

Page 89: ...gister 02A0 2090 QSER QDMA Secondary Event Register 02A0 2094 QSECR QDMA Secondary Event Clear Register 02A0 2098 02A0 21FF Reserved Shadow Region 1 Channel Registers 02A0 2200 ER Event Register 02A0 2204 ERH Event Register High 02A0 2208 ECR Event Clear Register 02A0 220C ECRH Event Clear Register High 02A0 2210 ESR Event Set Register 02A0 2214 ESRH Event Set Register High 02A0 2218 CER Chained E...

Page 90: ...ent Set Register High 02A0 2418 CER Chained Event Register 02A0 241C CERH Chained Event Register Hig 02A0 2420 EER Event Enable Register 02A0 2424 EERH Event Enable Register High 02A0 2428 EECR Event Enable Clear Register 02A0 242C EECRH Event Enable Clear Register High 02A0 2430 EESR Event Enable Set Register 02A0 2434 EESRH Event Enable Set Register High 02A0 2438 SER Secondary Event Register 02...

Page 91: ...Set Register High 02A0 2638 SER Secondary Event Register 02A0 263C SERH Secondary Event Register High 02A0 2640 SECR Secondary Event Clear Register 02A0 2644 SECRH Secondary Event Clear Register High 02A0 2648 02A0 264C Reserved 02A0 2650 IER Interrupt Enable Register 02A0 2654 IERH Interrupt Enable Register High 02A0 2658 IECR Interrupt Enable Clear Register 02A0 265C IECRH Interrupt Enable Clear...

Page 92: ...e Register High 02A0 2858 IECR Interrupt Enable Clear Register 02A0 285C IECRH Interrupt Enable Clear Register High 02A0 2860 IESR Interrupt Enable Set Register 02A0 2864 IESRH Interrupt Enable Set Register High 02A0 2868 IPR Interrupt Pending Register 02A0 286C IPRH Interrupt Pending Register High 02A0 2870 ICR Interrupt Clear Register 02A0 2874 ICRH Interrupt Clear Register High 02A0 2878 IEVAL ...

Page 93: ...ICR Interrupt Clear Register 02A0 2A74 ICRH Interrupt Clear Register High 02A0 2A78 IEVAL Interrupt Evaluate Register 02A0 2A7C Reserved 02A0 2A80 QER QDMA Event Register 02A0 2A84 QEER QDMA Event Enable Register 02A0 2A88 QEECR QDMA Event Enable Clear Register 02A0 2A8C QEESR QDMA Event Enable Set Register 02A0 2A90 QSER QDMA Secondary Event Register 02A0 2A94 QSECR QDMA Secondary Event Clear Reg...

Page 94: ...ister 02A0 2C94 QSECR QDMA Secondary Event Clear Register 02A0 2C98 02A0 2DFF Reserved Shadow Region 7 Channel Registers 02A0 2E00 ER Event Register 02A0 2E04 ERH Event Register High 02A0 2E08 ECR Event Clear Register 02A0 2E0C ECRH Event Clear Register High 02A0 2E10 ESR Event Set Register 02A0 2E14 ESRH Event Set Register High 02A0 2E18 CER Chained Event Register 02A0 2E1C CERH Chained Event Reg...

Page 95: ... ICRH Interrupt Clear Register High 02A0 2E78 IEVAL Interrupt Evaluate Register 02A0 2E7C Reserved 02A0 2E80 QER QDMA Event Register 02A0 2E84 QEER QDMA Event Enable Register 02A0 2E88 QEECR QDMA Event Enable Clear Register 02A0 2E8C QEESR QDMA Event Enable Set Register 02A0 2E90 QSER QDMA Secondary Event Register 02A0 2E94 QSECR QDMA Secondary Event Clear Register 02A0 2E98 02A0 2FFF Reserved Cop...

Page 96: ...Error Enable Register 02A2 0128 ERRCLR Error Clear Register 02A2 012C ERRDET Error Details Register 02A2 0130 ERRCMD Error Interrupt Command Register 02A2 0134 02A2 013C Reserved 02A2 0140 RDRATE Read Rate Register 02A2 0144 02A2 023C Reserved 02A2 0240 SAOPT Source Active Options Register 02A2 0244 SASRC Source Active Source Address Register 02A2 0248 SACNT Source Active Count Register 02A2 024C ...

Page 97: ...Register 2 02A2 0394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A2 0398 02A2 03BC Reserved 02A2 03C0 DFOPT3 Destination FIFO Options Register 3 02A2 03C4 DFSRC3 Destination FIFO Source Address Register 3 02A2 03C8 DFCNT3 Destination FIFO Count Register 3 02A2 03CC DFDST3 Destination FIFO Destination Address Register 3 02A2 03D0 DFBIDX3 Destination FIFO BIDX Register 3 02A2 03D...

Page 98: ...xy Register 0 02A2 8318 02A2 833C Reserved 02A2 8340 DFOPT1 Destination FIFO Options Register 1 02A2 8344 DFSRC1 Destination FIFO Source Address Register 1 02A2 8348 DFCNT1 Destination FIFO Count Register 1 02A2 834C DFDST1 Destination FIFO Destination Address Register 1 02A2 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A2 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A2 ...

Page 99: ...DFSRCBREF Destination FIFO Set Destination Address B Reference Register 02A3 0288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02A3 028C 02A3 02FC Reserved 02A3 0300 DFOPT0 Destination FIFO Options Register 0 02A3 0304 DFSRC0 Destination FIFO Source Address Register 0 02A3 0308 DFCNT0 Destination FIFO Count Register 0 02A3 030C DFDST0 Destination FIFO Destination Address...

Page 100: ...44 SASRC Source Active Source Address Register 02A3 8248 SACNT Source Active Count Register 02A3 824C SADST Source Active Destination Address Register 02A3 8250 SABIDX Source Active Source B Index Register 02A3 8254 SAMPPRXY Source Active Memory Protection Proxy Register 02A3 8258 SACNTRLD Source Active Count Reload Register 02A3 825C SASRCBREF Source Active Source Address B Reference Register 02A...

Page 101: ...Controller 4 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A4 0000 PID Peripheral Identification Register 02A4 0004 TCCFG EDMA3TC Configuration Register 02A4 0008 02A4 00FC Reserved 02A4 0100 TCSTAT EDMA3TC Channel Status Register 02A4 0104 02A4 011C Reserved 02A4 0120 ERRSTAT Error Register 02A4 0124 ERREN Error Enable Register 02A4 0128 ERRCLR Error Clear Register 02A4 012C ERRDET Error De...

Page 102: ...02A4 038C DFDST2 Destination FIFO Destination Address Register 2 02A4 0390 DFBIDX2 Destination FIFO BIDX Register 2 02A4 0394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A4 0398 02A4 03BC Reserved 02A4 03C0 DFOPT3 Destination FIFO Options Register 3 02A4 03C4 DFSRC3 Destination FIFO Source Address Register 3 02A4 03C8 DFCNT3 Destination FIFO Count Register 3 02A4 03CC DFDST3 De...

Page 103: ... DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0 02A4 8318 02A4 833C Reserved 02A4 8340 DFOPT1 Destination FIFO Options Register 1 02A4 8344 DFSRC1 Destination FIFO Source Address Register 1 02A4 8348 DFCNT1 Destination FIFO Count Register 1 02A4 834C DFDST1 Destination FIFO Destination Address Register 1 02A4 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A4 8354 DFMPPRXY1 Destinat...

Page 104: ...e 3 AET Interrupt 10 Unused Reserved 11 EMU_RTDXRX RTDX Receive Complete 12 EMU_RTDXTX RTDX Transmit Complete 13 IDMAINT0 IDMA Channel 0 Interrupt 14 IDMAINT1 IDMA Channel 1 Interrupt 15 FSEVT0 Frame Synchronization Event 0 16 FSEVT1 Frame Synchronization Event 1 17 FSEVT2 Frame Synchronization Event 2 18 FSEVT3 Frame Synchronization Event 3 19 FSEVT4 Frame Synchronization Event 4 20 FSEVT5 Frame ...

Page 105: ... GPIO Interrupt 7 53 GPINT8 GPIO Interrupt 8 53 GPINT9 GPIO Interrupt 9 55 GPINT10 GPIO Interrupt 10 56 GPINT11 GPIO Interrupt 11 57 GPINT12 GPIO Interrupt 12 58 GPINT13 GPIO Interrupt 13 59 GPINT14 GPIO Interrupt 14 60 GPINT15 GPIO Interrupt 15 61 TPCC_GINT EDMA Channel Global Completion Interrupt 62 TPCC_INT0 TPCC Completion Interrupt Mask 0 63 TPCC_INT1 TPCC Completion Interrupt Mask 1 64 TPCC_...

Page 106: ...Event 12 from Chip Interrupt Controller n 93 CICn_EVT13 System Event 13 from Chip Interrupt Controller n 94 Unused Reserved 95 Unused Reserved 96 INTERR Dropped CPU Interrupt Event 97 EMC_IDMAERR Invalid IDMA Parameters 98 Unused Reserved 99 Unused Reserved 100 EFINTA EFI Interrupt from Side A 101 EFIINTB EFI Interrupt from Side B 102 112 Unused Reserved 113 PMC_ED Single Bit Error Detected during...

Page 107: ...C and FSYNC events that are not otherwise provided to each C64x Megamodule The event controllers each include two event combiners to provide two combined events to each C64x Megamodule for use Each of the 16 event outputs from the controllers can select any of the 64 inputs or either of the two combined events to pass on to their respective C64x Megamodule Table 7 15 lists the system events that a...

Page 108: ... 2 47 AIF_PSEVT0 Packet Switched Transfer Event 0 48 AIF_PSEVT1 Packet Switched Transfer Event 1 49 AIF_PSEVT2 Packet Switched Transfer Event 2 50 AIF_PSEVT3 Packet Switched Transfer Event 3 51 AIF_PSEVT4 Packet Switched Transfer Event 4 52 AIF_PSEVT5 Packet Switched Transfer Event 5 53 AIF_PSEVT6 Packet Switched Transfer Event 6 54 AIF_BUFEVT AIF Capture Buffer Event 55 57 Unused Reserved 58 SEME...

Page 109: ...ization Event 26 19 FSEVT27 Frame Synchronization Event 27 20 FSEVT28 Frame Synchronization Event 28 21 RIOINT0 RapidIO Interrupt 0 22 RIOINT1 RapidIO Interrupt 1 23 RIOINT2 RapidIO Interrupt 2 24 RIOINT3 RapidIO Interrupt 3 25 RIOINT4 RapidIO Interrupt 4 26 RIOINT5 RapidIO Interrupt 5 27 RIOINT7 RapidIO Interrupt 7 28 MACINT 0 Ethernet EMAC Interrupt 29 MACRXINT 0 Ethernet EMAC Interrupt 30 MACTX...

Page 110: ...57 GPINT4 GPIO Event 58 CIC0_EVT14 CIC_EVT_o 14 from Chip Interrupt Controller 0 59 CIC0_EVT15 CIC_EVT_o 15 from Chip Interrupt Controller 0 60 CIC1_EVT14 CIC_EVT_o 14 from Chip Interrupt Controller 1 61 CIC1_EVT15 CIC_EVT_o 15 from Chip Interrupt Controller 1 62 CIC2_EVT14 CIC_EVT_o 14 from Chip Interrupt Controller 2 63 CIC2_EVT15 CIC_EVT_o 15 from Chip Interrupt Controller 2 110 Peripheral Info...

Page 111: ...IN MAX UNIT 1 tw NMIL Width of the NMI interrupt pulse low 6P ns 2 tw NMIH Width of the NMI interrupt pulse high 6P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns Figure 7 5 NMI Interrupt Timing Copyright 2008 2010 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 111 Submit Documentation Feedback Product Folder Link s TMS...

Page 112: ...power on reset 1 Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted driven low While POR is asserted all pins except RESETSTAT will be set to high impedance After the POR pin is de asserted driven high all Z group pins low group pins and high group pins are set to their reset state and will remain at their reset state until otherwise configured by t...

Page 113: ... on the Debug Advanced Resets System Reset menu in Code Composer Studio using the emulator System reset is also triggered by RIOINT 6 which is connected to the reset controller It is considered a soft reset meaning memory contents are maintained it does not affect the clock logic or the power control logic of the peripherals 1 The RESETSTAT pin goes low to indicate an internal reset is being gener...

Page 114: ...Read only n value after reset Figure 7 6 Reset Type Status Register RSTYPE Hex Address 029A 00E4 Table 7 19 Reset Type Status Register RSTYPE Field Descriptions BIT FIELD VALUE DESCRIPTION 31 4 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has not effect 3 SRST System Reset 0 System Reset was not the last reset to occur 1 System Reset was the last re...

Page 115: ...R or 12C ns XWRST high 1 If CORECLKSEL 0 C 1 SYSCLK N P frequency in ns 2 If CORECLKSEL 1 C 1 ALTCORECLK N P frequency in ns Table 7 21 Switching Characteristics Over Recommended Operating Conditions During Reset 1 see Figure 7 7 and Figure 7 8 NO MIN MAX UNIT 3 td PORH RSTATH Delay Time POR high to RESETSTAT high 21000C ns 5 td XWRSTH RSTATH Delay Time XWRST high to RESETSTAT high 35C ns 1 C 1 CP...

Page 116: ...R 2008 REVISED JULY 2010 www ti com Figure 7 8 Warm Reset Timing Figure 7 9 Warm Reset Timing 116 Peripheral Information and Electrical Specifications Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 117: ...s documented in this section are supported Furthermore only the bits within the registers described here are supported You should not write to any reserved memory location or change the value of reserved bits The Main and DDR PLLs are controlled by standard PLL Controller peripherals The PLL Controllers manage the clock ratios alignment and gating for the system clocks to the chip Figure 7 10 incl...

Page 118: ...of 333 MHz Please note that the data rate on the trace pins are 1 2 of this clock 7 8 1 2 PLL1 Controller Operating Modes The PLL1 controller has two modes of operation bypass mode and PLL mode The mode of operation is determined by the PLLEN bit of the PLL control register PLLCTL In PLL mode SYSREFCLK is generated from the device input clock CLKIN1 and the PLL multiplier PLLM In bypass mode CLKIN...

Page 119: ...20 Reserved 029A 0124 Reserved 029A 0128 Reserved 029A 012C Reserved 029A 0130 Reserved 029A 0134 Reserved 029A 0138 PLLCMD PLL Controller Command Register 029A 013C PLLSTAT PLL Controller Status Register 029A 0140 ALNCTL PLL Controller Clock Align Control Register 029A 0144 DCHANGE PLLDIV Ratio Change Status Register 029A 0148 Reserved 029A 014C Reserved 029A 0150 SYSTAT SYSCLK Status Register 02...

Page 120: ... W Read Write R Read only n value after reset Figure 7 11 PLL1 Control Register PLLCTL Hex Address 029A 0100 Table 7 25 PLL1 Control Register PLLCTL Field Descriptions Bit Field Value Description 31 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 Reserved Reserved Writes to this register must keep this bit as 0 6 Reserved Reserved The...

Page 121: ... Address 029A 0110 Table 7 26 PLL Multiplier Control Register PLLM Field Descriptions 1 Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 PLLM PLL multiplier bits Defines the input reference clock frequency multiplier 0h Bypass 3h x4 multiplier rate 4h x5 multiplier rate 1Eh x31 multiplier rate 1Fh x32...

Page 122: ...16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 D11EN Divider 11 enable bit 0 Divider 11 is disabled No clock output 1 Divider 11 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO 1 0 1Fh Divider ratio bits 0h 4h Reserved do not use 7h 31h 8 to 3...

Page 123: ...d Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 D13EN Divider 13 enable bit 0 Divider 13 is disabled No clock output 1 Divider 13 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO 0 1Fh Divider ratio ...

Page 124: ...erved bit location is always read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSET GO operation command for SYSCLK rate change and phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operatio...

Page 125: ...LLSTAT Hex Address 029A 013C Table 7 30 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSTAT GO operation status 0 GO operation is not in progress SYSCLK divide ratios are not being changed 1 GO operation is in progress SYSCLK divide ratios ar...

Page 126: ...during GO operation If SYS13 in DCHANGE is set to 1 SYSCLK13 switches to the new ratio immediately after the GOSET bit in PLLCMD is set 1 Align SYSCLK13 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set The SYSCLK13 ratio is set to the ratio programmed in the RATIO bit in PLLDIV13 11 Reserved 1 Reserved The reserved bit location is always read as 1 A value written to this fie...

Page 127: ...eld Descriptions Bit Field Value Description 31 13 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 12 SYS13 Identifies when the SYSCLK13 divide ratio has been modified 0 SYSCLK13 ratio has not been modified When GOSET is set SYSCLK13 will not be affected 1 SYSCLK13 ratio has been modified When GOSET is set SYSCLK13 will change to the ne...

Page 128: ...set Figure 7 19 SYSCLK Status Register SYSTAT Hex Address 029A 0150 Table 7 33 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 13 Reserved 1 Reserved The reserved bit location is always read as 1 A value written to this field has no effect 12 6 SYSnON SYSCLKn on status 0 SYSCLKn is gated 1 SYSCLKn is on 5 0 Reserved 1 Reserved The reserved bit location is always rea...

Page 129: ...ps CORECLKSEL 1 1 tc ALTCORECLK Cycle time ALTCORECLK N P 16 2 25 00 ns 2 tw ALTCORECLK Pulse duration ALTCORECLK N P high 0 4C ns 3 tw ALTCORECLKL Pulse duration ALTCORECLK N P low 0 4C ns 4 tt ALTCORECLK Transition time ALTCORECLK N P 50 1300 ps 5 tj ALTCORECLK Period Jitter peak to peak ALTCORECLK N P 100 ps SYSCLKOUT 1 tc CKO Cycle time SYSCLKOUT 10C 32C ns 2 tw CKOH Pulse duration SYSCLKOUT h...

Page 130: ... single side of the board without jumpers switches or components other than the ones shown For reduced PLL jitter maximize the spacing between switching signals and the PLL external components capacitors and the EMI filter The minimum CLKIN2 rise and fall times should also be observed Figure 7 21 PLL2 Block Diagram 7 9 1 PLL2 Controller Device Specific Information 7 9 1 1 Internal Clocks and Maxim...

Page 131: ...r up sequence see Section 7 7 Reset Controller and is locked by the time the RESETSTAT pin goes high It does not lose lock during any of the other resets 7 9 2 PLL2 Controller Input and Output Electrical Data Timing Table 7 36 Timing Requirements for DDRREFCLK N P 1 see Figure 7 22 NO PARAMETERS MIN MAX UNIT 1 tc DDRREFCLK Cycle time DDRREFCLK N P 15 25 ns 2 tw DDRREFCLKH Pulse duration DDRREFCLK ...

Page 132: ...2 memory controller on the C6474 device supports the following memory topologies 32 bit wide configuration interfacing to two 16 bit wide DDR2 SDRAM devices 16 bit wide configuration interfacing to a single 16 bit wide DDR2 SDRAM device A race condition may exist when certain masters write data to the DDR2 memory controller For example if master A passes a software message via a buffer in external...

Page 133: ...r 7000 0014 SDTIM2 DDR2 Memory Controller SDRAM Timing 2 Register 7000 0018 Reserved 7000 0020 BPRIO DDR2 Memory Controller Burst Priority Register 7000 0024 7000 004C Reserved 7000 0050 7000 0078 Reserved 7000 007C 7000 00BC Reserved 7000 00C0 7000 00E0 Reserved 7000 00E4 DMCCTL DDR2 Memory Controller Control Register 7000 00E8 7000 00EC Reserved 7000 00F0 DDR2IO Control Register DDR2 ODT control...

Page 134: ...t follow the board design guidelines outlined in the SPRAAW8 application report Table 7 38 Timing Requirements for DDRREFCLK N P 1 see Figure 7 23 NO PARAMETERS MIN MAX UNIT 1 tc DDRREFCLK Cycle time DDRREFCLK N P 15 25 ns 2 tw DDRREFCLKH Pulse duration DDRREFCLK N P high 0 4C ns 3 tw DDRREFCLKL Pulse duration DDRREFCLK N P low 0 4C ns 4 tt DDRREFCLK Transition time DDRREFCLK N P 50 1300 ps 5 tj D...

Page 135: ... the SDA and SCL pins The I2C modules on the C6474 may be used by the DSP to control local peripherals ICs DACs ADCs etc or may be used to communicate with other controllers in a system or to implement a user interface The I2C port supports Compatible with Philips I2C Specification Revision 2 1 January 2000 Fast Mode up to 400 Kbps no fail safe I O buffers Noise Filter to remove noise 50 ns or les...

Page 136: ...EVISED JULY 2010 www ti com Figure 7 24 I2C Module Block Diagram 136 Peripheral Information and Electrical Specifications Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 137: ... 02B0 4018 ICDRR I2C Data Receive Register 02B0 401C ICSAR I2C Slave Address Register 02B0 4020 ICDXR I2C Data Transmit Register 02B0 4024 ICMDR I2C Mode Register 02B0 4028 ICIVR I2C Interrupt Vector Register 02B0 402C ICEMDR I2C Extended Mode Register 02B0 4030 ICPSC I2C Prescaler Register 02B0 4034 ICPID1 I2C Peripheral Identification Register 1 Value 0x0000 0105 02B0 4038 ICPID2 I2C Peripheral ...

Page 138: ... 15 Cb 5 Capacitive load for each bus line 400 400 pF 1 The I2C pins SDA and SCL do not feature fail safe I O buffers These pins could potentially draw current when the device is powered down 2 A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement tsu SDA SCLH 250 ns must then be met This will automatically be the case if the device does not stretch the LOW p...

Page 139: ... SDAV Valid time SDA valid after SCL low for PC 0 0 0 9 ms bus devices 23 Tw SDAH Pulse duration SDA high between STOP and 4 7 1 3 ms START conditions 24 tr SDA Rise time SDA 1000 20 0 1Cb 1 300 ns 25 tr SDL Rise time SCL 1000 20 0 1Cb 1 300 ns 26 tf SDA Fall time SDA 300 20 0 1Cb 1 300 ns 27 tf SCL Fall time SCL 300 20 0 1Cb 1 300 ns 28 td SCLH SDAH Delay time SCL high to SDA high for STOP 4 0 6 ...

Page 140: ...he sample rate generator clock CLKSRG selection logical diagram A For more details see SYSCLK11 description in Section 7 8 1 1 Figure 7 27 Sample Rate Generator Clock CLKSRG 7 12 2 McBSP Peripheral Register Descriptions The memory map of the McBSP 0 registers is shown in Table 7 42 Table 7 42 McBSP 0 Registers HEX ADDRESS ACRONYM REGISTER NAME 028C 0000 DRR0 McBSP0 Data Receive Register via Config...

Page 141: ...ter via Configuration Bus 3400 0010 DXR1 McBSP1 Data Transmit Register via EDMA Bus 028D 0008 SPCR1 McBSP1 Serial Port Control Register 028D 000C RCR1 McBSP1 Receive Control Register 028D 0010 XCR1 McBSP1 Transmit Control Register 028D 0014 SRGR1 McBSP1 Sample Rate Generator Register 028D 0018 MCR1 McBSP1 Multichannel Control Register 028D 001C RCERE01 McBSP1 Enhanced Receive Channel Enable Regist...

Page 142: ...s CLKR ext 3 7 tsu DRV CKRL Setup time DR valid before CLKR low CLKR int 8 ns CLKR ext 0 9 8 th CKRL DRV Hold time DR valid after CLKR low CLKR int 3 ns CLKR ext 3 1 10 tsu FXH CKXL Setup time external FSX high before CLKX low CLKR int 9 ns CLKR ext 1 3 11 th CKXL FXH Hold time external FSX high after CLKX low CLKR int 6 ns CLKR ext 3 1 P 1 CPU Clock in ns 2 This parameter applies to the maximum M...

Page 143: ...nals is inverted then the timing references of that signal are also inverted 2 Minimum delay times also represent minimum output hold times 3 The CLKS signal is shared by both McBSP0 and McBSP1 on this device 4 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 5 C H or L S sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S sample rate genera...

Page 144: ...uirements for FSR When GSYNC 1 see Figure 7 29 NO MIN MAX UNIT 1 tsu FRH CKSH Setup time FSR high before CLKS high 4 ns 2 th CKSH FRH Hold time FSR high after CLKS high 4 ns Figure 7 29 FSR Timing When GSYNC 1 144 Peripheral Information and Electrical Specifications Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 145: ...ast data bit from CLKX low Disable time DX high impedance following 7 tdis FXH DXHZ 6P 3 18P 17 ns last data bit from FSX high 8 td FXL DXV Delay time FSX low to DX valid 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM...

Page 146: ...e following 6 tdis CKXL DXHZ 2 4 18P 3 30P 17 ns last data bit from CLKX low 7 td FXL DXV Delay time FSX low to DX valid H 2 H 4 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLKG...

Page 147: ...ast data bit from CLKX high Disable time DX high impedance following 7 tdis FXH DXHZ 6P 3 18P 17 ns last data bit from FSX high 8 td FXL DXV Delay time FSX low to DX valid 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKS...

Page 148: ...e following 6 tdis CKXH DXHZ 2 4 18P 3 30P 17 ns last data bit from CLKX high 7 td FXL DXV Delay time FSX low to DX valid L 2 L 4 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLK...

Page 149: ...nverting the frame CRC so that the transmitted frame will be detected as an error by the network The EMAC control module is the main interface between the device core processor the MDIO module and the EMAC module The relationship between these three components is shown in Figure 7 34 The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory ...

Page 150: ...ster 02C8 00B8 MACINTMASKSET MAC Interrupt Mask Set Register 02C8 00BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 02C8 00C0 02C8 00FC Reserved 02C8 0100 RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register 02C8 0104 RXUNICASTSET Receive Unicast Enable Set Register 02C8 0108 RXUNICASTCLEAR Receive Unicast Clear Register 02C8 010C RXMAXLEN Receive Maximum Length Registe...

Page 151: ...gister 02C8 020C RXPAUSEFRAMES Pause Receive Frames Register 02C8 0210 RXCRCERRORS Receive CRC Errors Register 02C8 0214 RXALIGNCODEERRORS Receive Alignment Code Errors Register 02C8 0218 RXOVERSIZED Receive Oversized Frames Register 02C8 021C RXJABBER Receive Jabber Frames Register02C80220 02C8 0220 RXUNDERSIZED Receive Undersized Frames Register 02C8 0224 RXFRAGMENTS Receive Frame Fragments Regi...

Page 152: ...tor Pointer Register 02C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 02C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 02C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 02C8 0620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register 02C8 0624 RX1HDP Receive t Channel 1 DMA Head Descriptor Pointer Register 02C8 0628 RX2H...

Page 153: ...eive Frames Register 02C8 0210 RXCRCERRORS Receive CRC Errors Register Total number of Frames Received with CRC Errors 02C8 0214 RXALIGNCODEERRORS Receive Alignment Code Errors register Total number of frames Received with alignment code errors 02C8 0218 RXOVERSIZED Receive Oversized Frames Register Total number of Oversized Frames Received 02C8 021C RXJABBER Receive Jabber Frames Register Total n...

Page 154: ... 02C8 0290 02C8 02FC Reserved Table 7 57 EMAC Descriptor Memory HEX ADDRESS ACRONYM REGISTER NAME 02C8 0000 02C8 3FFF EMAC Descriptor Memory Table 7 58 SGMII Control Registers HEX ADDRESS ACRONYM REGISTER NAME 02C4 0000 IDVER Identification and Version register 02C4 0004 SOFT_RESET Software Reset Register 02C4 0010 CONTROL Control Register 02C4 0014 STATUS Status Register 02C4 0018 MR_ADV_ABILITY ...

Page 155: ...S320C6474 Hardware Design Guide application report literature number SPRAAW7 specifies a complete EMAC anc SGMII interface solutions for the C6474 device as well as a list of compatible EMAC and SGMII devices TI has performed the simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution are met TI only supports designs that follow the board design guide...

Page 156: ...iption s The memory map of the MDIO is shown in Table 7 61 Table 7 61 MDIO Registers HEX ADDRESS ACRONYM REGISTER NAME 02C8 1800 VERSION MDIO Version Register 02C8 1804 CONTROL MDIO Control Register 02C8 1808 ALIVE MDIO PHY Alive Status Register 02C8 180C LINK MDIO PHY Link Status Register 02C8 1810 LINKINTRAW MDIO link Status Change Interrupt unmasked Register 02C8 1814 LINKINTMASKED MDIO link St...

Page 157: ...5 ns 4 tsu MDIO MDCLKH Setup time MDIO data input valid before MDCLK high 10 ns 5 th MDCLKH MDIO Hold time MDIO data input valid after MDCLK high 10 ns Figure 7 36 MDIO Input Timing Table 7 63 Switching Characteristics Over Recommended Operating Conditions for MDIO Outputs see Figure 7 37 NO MIN MAX UNIT 7 td MDCLKL MDIO Delay time MDCLK low to MDIO data output valid 100 ns Figure 7 37 MDIO Output...

Page 158: ...tion 7 15 1 1 Timer I O Selection Not all timer inputs and outputs are pinned out of the device The six timers have a flexible e g software controlled selection of timer inputs and outputs At the chip level there are four timer pins two input pins TIMI 1 0 and two output pins TIMO 1 0 Each timer input can be configured to be driven by either of the timer input pins or by an FSYNC event FSEVT 3 2 E...

Page 159: ...onfusion with respect to numbering a different convention is used in this document as shown in Table 7 64 Table 7 64 Timer Pin Naming TIMER SIGNAL NAME RENAMED TO DESCRIPTION n TINP12 TINPLn Timer n input event low half Used to drive lower 32 bit timer 64 bit timer Used in watchdog mode n TINP34 TINPHn Timer n input event high half Used to drive upper 32 bit timer Unused in 64 bit or watchdog mode...

Page 160: ...ved Reserved 23 22 TINPHSEL5 Input Select for TIMER 5 High 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 21 20 TINPLSEL5 Input Select for TIMER 5 Low 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 19 18 TINPHSEL4 Input Select for TIMER 4 High 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 17 16 TINPLSEL4 Input Select for TIMER 4 Low 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 15 14 TINPHSEL3 Input Select for TIMER 3 High 00 TIMI...

Page 161: ...lect for TIMER 1 High 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 5 4 TINPLSEL1 Input Select for TIMER 1 Low 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 3 2 TINPHSEL0 Input Select for TIMER 0 High 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 1 0 TINPLSEL0 Input Select for TIMER 0 Low 00 TIMI0 01 TIMI1 10 FSEVT2 11 FSEVT3 Copyright 2008 2010 Texas Instruments Incorporated Peripheral Information and Electrical Specifi...

Page 162: ...ter TOUTPSEL Table 7 66 Timer Output Selection Register TOUTPSEL Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 4 TOUTPSEL1 Output Select for TIMI1 0000 TOUTL0 0001 TOUTH0 0010 TOUTL1 0011 TOUTH1 0100 TOUTL2 0101 TOUTH2 0110 TOUTL3 0111 TOUTH3 1000 TOUTL4 1001 TOUTH5 1010 TOUTL5 1011 TOUTH5 Other Reserved 3 0 TOUTPSEL0 Output Select for TIMO0 0000 TOUTL0 0001 TOUTH0 0010 T...

Page 163: ...hdog Reset Selection Register WDRSTSEL Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 2 WRDSTSELn Reset Select for Watchdog Timer 0 TOUTnL does not cause WDRSTSEL to assert to the corresponding C64x megamodule 1 TOUTnL causes a reset of the corresponding C64x megamodule via the host reset port of the LPSC 7 15 2 Timers Peripheral Description s Table 7 68 Timer 0 Registers ...

Page 164: ...nter Register Low 0293 0014 TIMHI Timer 2 Counter Register High 0293 0018 PRDLO Timer 2 Period Register Low 0293 001C PRDHI Timer 2 Period Register High 0293 0020 TCR Timer 2 Control Register 0293 0024 TGCR Timer 2 Global Control Register 0293 0028 WDTCR Timer 2 Watchdog Timer Control Register 0293 002C Reserved 0293 0030 Reserved 0293 0034 0293 FFFF Reserved Table 7 71 Timer 3 Registers HEX ADDRE...

Page 165: ... 7 73 Timer 5 Registers HEX ADDRESS ACRONYM REGISTER NAME 0296 0000 PID Peripheral ID Register 0296 0004 EMUMGT_CLKSPD Timer 5 Emulation Management Clock Speed Register 0296 0008 Reserved 0296 000C Reserved 0296 0010 TIMLO Timer 5 Counter Register Low 0296 0014 TIMHI Timer 5 Counter Register High 0296 0018 PRDLO Timer 5 Period Register Low 0296 001C PRDHI Timer 5 Period Register High 0296 0020 TCR...

Page 166: ...Switching Characteristics Over Recommended Operating Conditions for Timer Outputs 1 see Figure 7 42 NO PARAMETER MIN MAX UNIT 3 tw TIMOH Pulse duration TIMO high 12C 3 ns 4 tw TIMOL Pulse duration TIMO low 12C 3 ns 1 If CORECLKSEL 0 C 1 SYSCLK NIP frequency in ns If CORECLKSEL 1 C 1 ALTCORECLK N P frequency in ns Figure 7 42 Timer Timing 166 Peripheral Information and Electrical Specifications Cop...

Page 167: ...ng hard decisions or soft decisions Communications between the VCP2 and the CPU are carried out through the EDMA3 controller The VCP2 supports Unlimited frame sizes Code rates 3 4 1 2 1 3 1 4 and 1 5 Constraint lengths 5 6 7 8 and 9 Programmable encoder polynomials Programmable reliability and convergence lengths Hard and soft decoded decisions Tail and convergent modes Yamamoto logic Tail biting ...

Page 168: ...t Register 1 5800 0050 5800 007C Reserved 5800 0080 N A VCPWBM VCP2 branch metrics write FIFO Register 5800 0084 5800 009C Reserved 5800 00C0 N A VCPRDECS VCP2 decisions read FIFO Register N A 02B8 0018 VCPEXE VCP2 execution Register N A 02B8 0020 VCPEND VCP2 Endian mode Register N A 02B8 0040 VCPSTAT0 VCP2 Status Register 0 N A 02B8 0044 VCPSTAT1 VCP2 Status Register 1 N A 02B8 0050 VCPERR VCP2 e...

Page 169: ...iterations The SNR stopping criteria algorithm The CRC stopping criteria algorithm For more detailed information on the TCP2 see the TMS320C6474 DSP Turbo Decoder Coprocessor 2 TCP2 Reference Guide literature number SPRUG21 7 17 2 TCP2 Peripheral Register Description s Table 7 78 TCP2 Registers EDMA BUS HEX ADDRESS RANGE CONFIGURATION BUS HEX ACRONYM REGISTER NAME ADDRESS RANGE 5000 0000 TCPIC0 TC...

Page 170: ...cratch Pad Memory 5008 0000 N A T0 TCP2 Beta State Memory 5009 0000 N A C0 TCP2 CRC Memory 500A 0000 N A B0 TCP2 Beta Prolog Memory 500B 0000 N A A0 TCP2 Alpha Prolog Memory N A 02BA 0000 TCPPID TCP2 Peripheral Identification Register Value 0x0002 1101 N A 02BA 004C TCPEXE TCP2 Execute Register N A 02BA 0050 TCPEND TCP2 Endian Register N A 02BA 0060 TCPERR TCP2 Error Register N A 02BA 0068 TCPSTAT...

Page 171: ...ll SRIO interface timings in this solution are met The complete SRIO system solution is documented in the TMS320C6474 DSP SERDES Implementation Guidelines application report literature number SPRAAW9 TI only supports designs that follow the board design guidelines outlined in the SPRAAW9 application report The Serial RapidIO peripheral is a master peripheral in the TCI6487 8 DSP It conforms to the...

Page 172: ... 0 CFG Register 02D0 0104 RIO_SERDES_CFGRX1_CNTL RapidIO SerDes RX Channel 1 CFG Register 02D0 0108 RIO_SERDES_CFGRX2_CNTL RapidIO SerDes RX Channel 2 CFG Register 02D0 010C RIO_SERDES_CFGRX3_CNTL RapidIO SerDes RX Channel 3 CFG Register 02D0 0110 RIO_SERDES_CFGTX0_CNTL RapidIO SerDes TX Channel 0 CFG Register 02D0 0114 RIO_SERDES_CFGTX1_CNTL RapidIO SerDes TX Channel 1 CFG Register 02D0 0118 RIO_...

Page 173: ...er 2 02D0 0298 02D0 029C Reserved 02D0 02A0 DOORBELL2_ICRR DOORBELL2 Interrupt Condition Routing Register 02D0 02A4 DOORBELL2_ICRR2 DOORBELL 2 Interrupt Condition Routing Register 2 02D0 02A8 02D0 02AC Reserved 02D0 02B4 DOORBELL3_ICRR2 DOORBELL 3 Interrupt Condition Routing Register 2 02D0 02B8 02D0 02BC Reserved 02D0 02C0 RX_CPPI _ICRR Receive CPPI Interrupt Condition Routing Register 02D0 02C4 ...

Page 174: ...1 Control Reg3 Register 02D0 0410 RIO_LSU1_Reg4 RapidIO LSU1 Control Reg4 Register 02D0 0414 RIO_LSU1_Reg5 RapidIO LSU1 Control Reg5 Register 02D0 0418 RIO_LSU1_Reg6 RapidIO LSU1 Control Reg6 Register 02D0 041C RIO_LSU1_FLOW_MASKS RapidIO Core0 LSU Congestion Control Flow Mask Register 02D0 0420 RIO_LSU2_Reg0 RapidIO LSU2 Control Reg0 Register 02D0 0424 RIO_LSU2_Reg1 RapidIO LSU2 Control Reg1 Regi...

Page 175: ...A Head Descriptor Pointer Register 02D0 0530 RIO_Queue12_TxDMA_HDP RapidIO Queue12 TX DMA Head Descriptor Pointer Register 02D0 0534 RIO_Queue13_TxDMA_HDP RapidIO Queue13 TX DMA Head Descriptor Pointer Register 02D0 0538 RIO_Queue14_TxDMA_HDP RapidIO Queue14 TX DMA Head Descriptor Pointer Register 02D0 053C RIO_Queue15_TxDMA_HDP RapidIO Queue15 TX DMA Head Descriptor Pointer Register 02D0 0540 RIO...

Page 176: ...gister 02D0 0620 RIO_Queue8_RxDMA_HDP RapidIO Queue8 RX DMA Head Descriptor Pointer Register 02D0 0624 RIO_Queue9_RxDMA_HDP RapidIO Queue9 RX DMA Head Descriptor Pointer Register 02D0 0628 RIO_Queue10_RxDMA_HDP RapidIO Queue10 RX DMA Head Descriptor Pointer Register 02D0 062C RIO_Queue11_RxDMA_HDP RapidIO Queue11 RX DMA Head Descriptor Pointer Register 02D0 0630 RIO_Queue12_RxDMA_HDP RapidIO Queue...

Page 177: ...7EC RIO_TX_QUEUE_CNTL3 RapidIO TX Queue Control 3 Register 02D0 07F0 02D0 07FC Reserved 02D0 0800 RXU_MAP_L0 Mailbox to Queue Mapping Register L0 02D0 0804 RXU_MAP_H0 Mailbox to Queue Mapping Register H0 02D0 0808 RXU_MAP_L1 Mailbox to Queue Mapping Register L1 02D0 080C RXU_MAP_H1 Mailbox to Queue Mapping Register H1 02D0 0810 RXU_MAP_L2 Mailbox to Queue Mapping Register L2 02D0 0814 RXU_MAP_H2 M...

Page 178: ...ster L23 02D0 08BC RXU_MAP_H23 Mailbox to Queue Mapping Register H23 02D0 08C0 RXU_MAP_L24 Mailbox to Queue Mapping Register L24 02D0 08C4 RXU_MAP_H24 Mailbox to Queue Mapping Register H24 02D0 08C8 RXU_MAP_L25 Mailbox to Queue Mapping Register L25 02D0 08CC RXU_MAP_H25 Mailbox to Queue Mapping Register H25 02D0 08D0 RXU_MAP_L26 Mailbox to Queue Mapping Register L26 02D0 08D4 RXU_MAP_H26 Mailbox t...

Page 179: ...R Local Configuration Space Base Address 1 02D0 1060 BASE_ID Base Device ID CSR 02D0 1064 Reserved 02D0 1068 HOST_BASE_ID_LOCK Host Base Device ID Lock CSR 02D0 106C COMP_TAG Component Tag CSR 02D0 1070 02D0 10FC Reserved 02D0 1100 SP_MB_HEAD 1x 4x LP_Serial Port Maintenance Block Header 02D0 1104 02D0 111C Reserved 02D0 1120 SP_LT_CTL Port Link Time Out Control CSR 02D0 1124 SP_RT_CTL Port Respon...

Page 180: ...SP0_ERR_ATTR_CAPT_DBG0 Port 0 Attributes Error Capture CSR 0 02D0 204C SP0_ERR_CAPT_DBG1 Port 0 Packet Control Symbol Error Capture CSR 1 02D0 2050 SP0_ERR_CAPT_DBG2 Port 0 Packet Control Symbol Error Capture CSR 2 02D0 2054 SP0_ERR_CAPT_DBG3 Port 0 Packet Control Symbol Error Capture CSR 3 02D0 2058 SP0_ERR_CAPT_DBG4 Port 0 Packet Control Symbol Error Capture CSR 4 02D0 205C 02D0 2064 Reserved 02...

Page 181: ...IP_MODE Port IP Mode CSR 02D1 2008 IP_PRESCAL Port IP Prescaler Register 02D1 200C Reserved 02D1 2010 SP_IP_PW_IN_CAPT0 Port Write In Capture CSR Register 0 02D1 2014 SP_IP_PW_IN_CAPT1 Port Write In Capture CSR Register 1 02D1 2018 SP_IP_PW_IN_CAPT2 Port Write In Capture CSR Register 2 02D1 201C SP_IP_PW_IN_CAPT3 Port Write In Capture CSR Register 3 02D1 2020 02D1 3FFC Reserved 02D1 4000 SP0_RST_O...

Page 182: ...F Reserved 02D2 1000 02DF FFFF Reserved 7 18 3 Serial RapidIO Electrical Data Timing Serial RapidIO is electrically compliant with the RapidIO Interconnect Specification Part VI Physical Layer 1x 4x LP Serial Specification Revision 1 2 Table 7 80 Timing Requirements for SRIOSGMIIREFCLK N P 1 see Figure 7 43 NO PARAMETERS MIN MAX UNIT 1 tc SRIOSGMIIREFCLK Cycle time SRIOSGMIIREFCLK N P 3 2 8 ns 2 t...

Page 183: ...ster 02B0 0024 SET_RIS_TRIG GPIO Set Rising Edge Interrupt Register 02B0 0028 CLR_RIS_TRIG GPIO Clear Rising Edge Interrupt Register 02B0 002C SET_FAL_TRIG GPIO Set Falling Edge Interrupt Register 02B0 0030 CLR_FAL_TRIG GPIO Clear Falling Edge Interrupt Register 02B0 008C Reserved 02B0 0090 02B0 00FF Reserved 02B0 0100 02B0 3FFF Reserved 7 19 2 GPIO Electrical Data Timing Table 7 82 Timing Require...

Page 184: ...n generate events such as halting the processor or triggering the trace capture Counters count the occurrence of an event or cycles for performance monitoring State Sequencing allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences For more information on AET see the following documents Using Advanced Event Triggering to Find and ...

Page 185: ...AX UNITS 1 tw EMUnH Pulse duration EMUn high 3 0 6 1 ns 1 tw EMUnH 90 Pulse duration EMUn high detected at 90 VOH 1 5 ns 1a tw TCKH Pulse width time TCK high 8 ns 1b tw TCKL Pulse width time TCK low 8 ns 2 tw EMUnL Pulse duration EMUn low 3 0 6 1 ns 2 tw EMUnL 10 Pulse duration EMUn low detected at 10 VOH 1 5 ns 3 tsko EMUn Output Skew time time delay difference between EMU pins configured as 500 ...

Page 186: ...TRST will always be asserted upon power up and the DSP s internal emulation logic will always be properly initialized when this pin is not routed out JTAG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST When using this type of JTAG controller assert TRST to initia...

Page 187: ... th TCKH EMUn Hold time EMUn input valid after TCK high 1 5 ns 4 td TCKH EMUn Delay time TCK high to EMUn output valid 3 16 5 ns 5 tpoz EMUn Propagation delay from output to high impedance 3 16 5 ns 6 tpzo EMUn Propagation delay from high impedance to output 3 16 5 ns Figure 7 47 HS RTDX Timing Copyright 2008 2010 Texas Instruments Incorporated Peripheral Information and Electrical Specifications ...

Page 188: ...er 02B4 0108 SEM_DIRECT2 Semaphore Direct2 Register 02B4 010C SEM_DIRECT3 Semaphore Direct3 Register 02B4 0110 SEM_DIRECT4 Semaphore Direct4 Register 02B4 0114 SEM_DIRECT5 Semaphore Direct5 Register 02B4 0118 SEM_DIRECT6 Semaphore Direct6 Register 02B4 011C SEM_DIRECT7 Semaphore Direct7 Register 02B4 0120 SEM_DIRECT8 Semaphore Direct8 Register 02B4 0124 SEM_DIRECT9 Semaphore Direct9 Register 02B4 ...

Page 189: ...8 Semaphore Indirect18 Register 02B4 024C SEM_INDIRECT19 Semaphore Indirect19 Register 02B4 0250 SEM_INDIRECT20 Semaphore Indirect20 Register 02B4 0254 SEM_INDIRECT21 Semaphore Indirect21 Register 02B4 0258 SEM_INDIRECT22 Semaphore Indirect22 Register 02B4 025C SEM_INDIRECT23 Semaphore Indirect23 Register 02B4 0260 SEM_INDIRECT24 Semaphore Indirect24 Register 02B4 0264 SEM_INDIRECT25 Semaphore Ind...

Page 190: ...RY26 Semaphore Query26 Register 02B4 036C SEM_QUERY27 Semaphore Query27 Register 02B4 0370 SEM_QUERY28 Semaphore Query28 Register 02B4 0374 SEM_QUERY29 Semaphore Query29 Register 02B4 0378 SEM_QUERY30 Semaphore Query30 Register 02B4 037C SEM_QUERY31 Semaphore Query31 Register 02B4 0400 SEM_FLAG0 Semaphore Flag0 Register for C64x Core0 02B4 0404 SEM_FLAG1 Semaphore Flag1 Register for C64x Core1 02B...

Page 191: ... Transmit Signal Pairs PIN NAMES I O NUMBER DESCRIPTION AIFTXN 5 0 OUT 6 Antenna Interface Links 0 5 Transmit Neg Data Lines AIFTXP 5 0 OUT 6 Antenna Interface Links 0 5 Transmit Pos Data Lines AIFRXN 5 0 IN 6 Antenna Interface Links 0 5 Receive Neg Data Lines AIFRXP 5 0 IN 6 Antenna Interface Links 0 5 Receive Pos Data Lines 7 22 1 Antenna Interface System AIF Register Description s Table 7 89 An...

Page 192: ...gister B 02BC 8888 RM_LINK_STSC RX MAC Link Status Register C 02BC 888C RM_LINK_STSD RX MAC Link Status Register D 02BC 8890 02BC 8FFC Reserved 02BC 9000 RM_LINK2_CFG RX MAC Link 2 Configuration Register 02BC 9004 RM_LINK2_PI_OFFSET_CFG RX MAC Link 2 Pi Offset Register 02BC 9008 RM_LINK2_LOS_THOLD_CFG RX MAC Link 2 LOS Threshold Register 02BC 900C 02BC 97FC Reserved 02BC 9800 RM_LINK3_CFG RX MAC L...

Page 193: ... 02BC E080 TM_LINK4_STS TX MAC Link 4 Status Register 02BC E084 02BC E7FC Reserved 02BC E800 TM_LINK5_0CFG TX MAC Link 5 Configuration Register 0 02BC E804 TM_LINK5_1CFG TX MAC Link 5 Configuration Register 1 02BC E808 TM_LINK5_2CFG TX MAC Link 5 Configuration Register 2 02BC E80C 02BC E87C Reserved 02BC E880 TM_LINK5_STS TX MAC Link 5 Status Register 02BC E884 02BC FFFC Reserved 02BD 0000 02BD 3F...

Page 194: ...nk 4 Header Error Status Register 3 02BD 6018 02BD 67FC Reserved 02BD 6800 AG_LINK5_CFG AG Link 5 Configuration Register 02BD 6804 AG_LINK5_STS AG Link 5 Status Register 02BD 6808 AG_LINK5_HDR_ERR_STSA AG Link 5 Header Error Status Register 0 02BD 680C AG_LINK5_HDR_ERR_STSB AG Link 5 Header Error Status Register 1 02BD 6810 AG_LINK5_HDR_ERR_STSC AG Link 5 Header Error Status Register 2 02BD 6814 A...

Page 195: ...CNT1_STS Data Buffer Outbound DMA Count 1 Register 02BE 3054 DB_OUT_DMA_CNT2_STS Data Buffer Outbound DMA Count 2 Register 02BE 3058 DB_IN_DMA_DEPTH_STS Data Buffer Inbound DMA Burst Available Register 02BE 305C DB_OUT_DMA_DEPTH_STS Data Buffer Outbound DMA Burst Available Register 02BE 3060 DB_OUT_PKTSW_STS Data Buffer Outbound Packet Switched FIFO Status Register 02BE 3064 DB_OUT_PKTSW_DEPTH_STS...

Page 196: ...er Outbound Packet Switched FIFO10 Tail Pointer 02BE 30EC DB_OUT_PKTSW_TAIL11_STS Data Buffer Outbound Packet Switched FIFO11 Tail Pointer 02BE 30F0 DB_OUT_PKTSW_TAIL12_STS Data Buffer Outbound Packet Switched FIFO12 Tail Pointer 02BE 30F4 DB_OUT_PKTSW_TAIL13_STS Data Buffer Outbound Packet Switched FIFO13 Tail Pointer 02BE 30F8 DB_OUT_PKTSW_TAIL14_STS Data Buffer Outbound Packet Switched FIFO14 T...

Page 197: ...Select Register 02BE 700C PD_TYPE_CIR_LUT_CFG Protocol Decoder Type CirSw Capture Enable LUT Register 02BE 7010 PD_TYPE_PKT_LUT_CFG Protocol Decoder Type PktSw Capture Enable LUT Register 02BE 7014 PD_TYPE_ERR_LUT_CFG Protocol Decoder Type Error Register 02BE 7018 02BE 77FC Reserved 02BE 7800 PD_ADR_LUT Protocol Decoder Address Look Up Table Register 02BE 7804 02BE 7FFC Reserved 02BE 8000 PE_LINK0...

Page 198: ...sion Rule Terminal Count 2 and 3 02BE 9814 02BE 99FC Reserved 02BE 9A00 02BE 9B4C PE_LINK3_84CNT_LUT PE 84 Count LUT RAM 02BE 9B50 02BE 9BFC Reserved 02BE 9C00 02BE 9C50 PE_LINK3_ID_LUT0 PE Identity LUT Part 0 RAM 02BE 9C54 02BE 9CFC Reserved 02BE 9D00 02BE 9D50 PE_LINK3_ID_LUT1 PE Identity LUT Part 1 RAM 02BE 9D54 02BE 9FFC Reserved 02BE A000 PE_LINK4_84_EN_LUT0_CFG PE 84 Count Message Enable bit...

Page 199: ...MSK_SET_B_EV1 EE Link 0 AI_EVENT 1 Interrupt Source Mask Set Register B 02BF 0028 EE_LINK0_MSK_CLR_A_EV0 EE Link 0 AI_EVENT 0 Interrupt Source Mask Clear Register A 02BF 002C EE_LINK0_MSK_CLR_B_EV0 EE Link 0 AI_EVENT 0 Interrupt Source Mask ClearRegister B 02BF 0030 EE_LINK0_MSK_CLR_A_EV1 EE Link 0 AI_EVENT 1 Interrupt Source Mask Clear Register A 02BF 0034 EE_LINK0_MSK_CLR_B_EV1 EE Link 0 AI_EVEN...

Page 200: ... 02BF 1024 EE_LINK2_MSK_SET_B_EV1 EE Link 2 AI_EVENT 1 Interrupt Source Mask Set Register B 02BF 1028 EE_LINK2_MSK_CLR_A_EV0 EE Link 2 AI_EVENT 0 Interrupt Source Mask Clear Register A 02BF 102C EE_LINK2_MSK_CLR_B_EV0 EE Link 2 AI_EVENT 0 Interrupt Source Mask Clear Register B 02BF 1030 EE_LINK2_MSK_CLR_A_EV1 EE Link 2 AI_EVENT 1 Interrupt Source Mask Clear Register A 02BF 1034 EE_LINK2_MSK_CLR_B_...

Page 201: ..._MSK_SET_B_EV1 EE Link 4 AI_EVENT 1 Interrupt Source Mask Set Register B 02BF 2028 EE_LINK4_MSK_CLR_A_EV0 EE Link 4 AI_EVENT 0 Interrupt Source Mask Clear Register A 02BF 202C EE_LINK4_MSK_CLR_B_EV0 EE Link 4 AI_EVENT 0 Interrupt Source Mask Clear Register B 02BF 2030 EE_LINK4_MSK_CLR_A_EV1 EE Link 4 AI_EVENT 1 Interrupt Source Mask Clear Register A 02BF 2034 EE_LINK4_MSK_CLR_B_EV1 EE Link 4 AI_EV...

Page 202: ... 2 Link Interrupt Mask Clear Register A 02BF 3150 EE_EV2_LINK_MSK_CLR_B Event 2 Link Interrupt Mask Clear Register B 02BF 3154 EE_COMMON_MSK_CLR_EV2 Event Enable 2 Common Interrupt Mask Clear Register 02BF 3158 EE_EV3_LINK_MSK_CLR_A Event 3 Link Interrupt Mask Clear Register A 02BF 315C EE_EV3_LINK_MSK_CLR_B Event 3 Link Interrupt Mask Clear Register B 02BF 3160 EE_COMMON_MSK_CLR_EV3 Event Enable ...

Page 203: ...ended ALTFSYNCCLK and ALTFSYNCPULSE inputs to drive the timers Table 7 90 FSYNC Event Connections C64x C64x C64x MODULE EVENTS MEGAMODULE MEGAMODULE MEGAMODULE CIC0 CIC1 CIC2 TPCC CIC3 TIMER AIF CORE 0 CORE 1 CORE 2 FSEVT0 X X X X FSEVT1 X X X X X FSEVT2 X X X X X FSEVT3 X X X X X FSEVT4 X X X X FSEVT5 X X X X FSEVT6 X X X X FSEVT7 X X X X FSEVT8 X X X X FSEVT9 X X X X FSEVT10 X X X X FSEVT11 X X ...

Page 204: ...ter 0280 0094 ERR_CLEAR_MASK_0 FSYNC ERR CLEAR MASK 0 Register 0280 0098 ERR_CLEAR_MASK_1 FSYNC ERR CLEAR MASK 1 Register 0280 009C ERR_INT_MASK_0 FSYNC ERR INT MASK 0 Register 0280 0100 RP3TC FSYNC RP3 Terminal Count Entry 0280 0128 TOD1 FSYNC TOD Capture Register 1 0280 012C FSYNC_TOD2 FSYNC TOD Capture Register 2 0280 0130 RP31 FSYNC RP3 Capture Register 1 0280 0134 RP32 FSYNC RP3 Capture Regis...

Page 205: ...gh or low 0 4 tc FSCLK 0 6 tc FSCLK ns 3 tu FSPLS Setup time ALTFSYNCPULSE high before ALTFSYNCCLK high 2 ns 4 th FSPLS Hold time ALTFSYNCPULSE low after ALTFSYNCCLK high 2 ns 5 tj FSCLK Period Jitter peak to peak FSYNCCLK N P 0 025 x tc ns Figure 7 48 FSYNC Clock and Synchronization Timing Figure 7 49 Alternate FSYNC Clock and Synchronization Timing Figure 7 50 TRT Clock and Synchronization Timin...

Page 206: ...ing Conditions for SMFRAMECLK 1 see Figure 7 51 NO PARAMETER MIN MAX UNIT 2 tc FSCLK Pulse duration SMFRAMECLK high or low 4C ns 1 C FSCLK Figure 7 51 SMFRAMECLK Timing 206 Peripheral Information and Electrical Specifications Copyright 2008 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320C6474 ...

Page 207: ... 1 RΘJC Junction to case 0 30 N A 2 RΘJB Junction to board 6 5 N A 1 A heatsink is required for proper device operation 2 m s meters per second 8 2 Packaging Information The following packaging information reflects the most current released data available for the designated device s This data is subject to change without notice and without revision of this document Copyright 2008 2010 Texas Instru...

Page 208: ... defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This compon...

Page 209: ...PACKAGE OPTION ADDENDUM www ti com 25 Sep 2010 Addendum Page 2 ...

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Page 213: ...ch statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications o...

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