Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
8
7
6
2
1
CLKX
FSX
DX
DR
TMS320C6474
www.ti.com
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Table 7-47. Timing Requirements for McBSP as SPI Master: CLKSTP = 10b, CLKXP = 0
(1)
(see
Figure 7-30
)
MASTER
SLAVE
NO.
UNIT
MIN
MAX
MIN
MAX
4
t
su(DRV-CKXL)
Setup time, DR valid before CLKX low
12
2 - 18P
ns
5
t
h(CKXL-DRV)
Hold time, DR valid after CLKX low
4
5 + 36P
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-48. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master: CLKSTP = 10b, CLKXP = 0
(1)
(see
Figure 7-30
)
MASTER
(2)
SLAVE
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
t
h(CKXL-FXL)
Hold time, FSX low after CLKX low
(3)
T - 2
T + 3
ns
2
t
d(FXL-CKXH)
Delay time, FSX low to CLKX high
(4)
L - 2
L + 3
ns
3
t
d(CKXH-DXV)
Delay time, CLKX high to DX valid
-2
4
18P + 2.8
30P + 17
ns
Disable time, DX high impedance following
6
t
dis(CKXL-DXHZ)
L - 2
L + 3
ns
last data bit from CLKX low
Disable time, DX high impedance following
7
t
dis(FXH-DXHZ)
6P + 3
18P + 17
ns
last data bit from FSX high
8
t
d(FXL-DXV)
Delay time, FSX low to DX valid
12P + 2
24P + 17
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2)
S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = ( 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = ( 1)/2 * S if CLKGDV is odd
(3)
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4)
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
Figure 7-30. McBSP Timing as SPI Master: CLKSTP = 10b, CLKXP = 0
Copyright © 2008–2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
145
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