TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
www.ti.com
Table 7-78. TCP2 Registers (continued)
EDMA BUS HEX ADDRESS RANGE
CONFIGURATION BUS HEX
ACRONYM
REGISTER NAME
ADDRESS RANGE
5000 0048
-
TCPOUT2
TCP2 Output Parameters Register 2
5001 0000
N/A
X0
TCP2 Data/Sys and Parity Memory
5003 0000
N/A
W0
TCP2 Extrinsic Mem 0
5004 0000
N/A
W1
TCP2 Extrinsic Mem 1
5005 0000
N/A
I0
TCP2 Interleaver Memory
5006 0000
N/A
O0
TCP2 Output/Decision Memory
5007 0000
N/A
S0
TCP2 Scratch Pad Memory
5008 0000
N/A
T0
TCP2 Beta State Memory
5009 0000
N/A
C0
TCP2 CRC Memory
500A 0000
N/A
B0
TCP2 Beta Prolog Memory
500B 0000
N/A
A0
TCP2 Alpha Prolog Memory
N/A
02BA 0000
TCPPID
TCP2 Peripheral Identification
Register [Value: 0x0002 1101]
N/A
02BA 004C
TCPEXE
TCP2 Execute Register
N/A
02BA 0050
TCPEND
TCP2 Endian Register
N/A
02BA 0060
TCPERR
TCP2 Error Register
N/A
02BA 0068
TCPSTAT
TCP2 Status Register
N/A
02BA 0070
TCPEMU
TCP2 Emulation Register
N/A
02BA 005C - 02BB FFFF
-
Reserved
170
Peripheral Information and Electrical Specifications
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