1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
1
0
2 3
0 1 2 3 4 5 6 7 8 91011
0 1 2 3 4 5 6 7 8 91011
T
OUTL
T
OUTH
TINPL
TINPH
Timer64
5
T
OUTL
T
OUTH
TINPL
TINPH
Timer64
4
T
OUTL
T
OUTH
TINPL
TINPH
Timer64
3
T
OUTL
T
OUTH
TINPL
TINPH
Timer642
2
T
OUTL
T
OUTH
TINPL
TINPH
Timer64
1
T
OUTL
T
OUTH
TINPL
TINPH
Timer64
0
FSEVT2
FSEVT3
TINPHSEL 0
TINPLSEL 0
TINPHSEL 1
TINPLSEL 1
TINPHSEL 2
TINPLSEL 2
TINPHSEL 3
TINPLSEL 3
TINPHSEL 4
TINPLSEL 4
TINPHSEL 5
TINPLSEL 5
TOUTSEL 1
TOUTSEL 0
32
CFG SCR
(SCR F)
TIMI0
TIMI1
TIMO0
TIMO1
vbusp
Timer Pin Manager
(TPMGR)
SYSCLK/6
TMS320C6474
www.ti.com
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Figure 7-38. Timer Manager Block Diagram
Note that the TMS320C6474 DSP 64-Bit Timer User’s Guide (literature number
SPRUG18
) uses different
labels for its inputs and outputs. To avoid confusion with respect to numbering, a different convention is
used in this document, as shown in
Table 7-64
.
Table 7-64. Timer Pin Naming
TIMER
SIGNAL NAME
RENAMED TO
DESCRIPTION
n
TINP12
TINPLn
Timer n input event (low half). Used to drive lower 32-bit timer, 64-bit timer.
Used in watchdog mode.
n
TINP34
TINPHn
Timer n input event (high half). Used to drive upper 32-bit timer. Unused in
64-bit or watchdog modes.
n
TOUT12
TOUTLn
Timer n output (low half). Driven by lower 32-bit timer, 64-bit timer, or
watchdog timer as either a pulse or waveform.
n
TOUT34
TOUTHn
Timer n output (high half). Driven by upper 32-bit timer as either a pulse or
waveform. Unused in 64-bit or watchdog modes.
7.15.1.1.1 Timer Input Selection Register (TINPSEL)
Timer input selection is handled in the Timer input selection register (TINPSEL). The TINPSEL register is
shown in
Figure 7-39
and described in
Table 7-65
.
Copyright © 2008–2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
159
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