Texas Instruments MSP430F5333, Manual

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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333
www.ti.com SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015
6.5 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence (see
Table 6-3 ).
Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F533x Configurations
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up, External Reset
WDTIFG, KEYV (SYSRSTIV)
(1) (2)
Reset 0FFFEh 63, highest
Watchdog Time-out, Key Violation
Flash Memory Key Violation
System NMI
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access
JMBOUTIFG (SYSSNIV)
(1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG
(Non)maskable 0FFFAh 61
Oscillator Fault (SYSUNIV)
(1) (2)
Flash Memory Access Violation
Comp_B Comparator B interrupt flags (CBIV)
(1) (3)
Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0
(3)
Maskable 0FFF6h 59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
Timer TB0 Maskable 0FFF4h 58
TB0IFG (TBIV)
(1) (3)
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)
(1) (3)
Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)
(1) (3)
Maskable 0FFEEh 55
ADC12_A ADC12IFG0 to ADC12IFG15 (ADC12IV)
(1) (3)
Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0
(3)
Maskable 0FFEAh 53
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
Timer TA0 Maskable 0FFE8h 52
TA0IFG (TA0IV)
(1) (3)
LDO-PWR LDOOFFIG, LDOONIFG, LDOOVLIFG Maskable 0FFE6h 51
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA Maskable 0FFE4h 50
DMA4IFG, DMA5IFG (DMAIV)
(1) (3)
Timer TA1 TA1CCR0 CCIFG0
(3)
Maskable 0FFE2h 49
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
Timer TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV)
(1) (3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)
(1) (3)
Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)
(1) (3)
Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)
(1) (3)
Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)
(1) (3)
Maskable 0FFD8h 44
Reserved Reserved Maskable 0FFD6h 43
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B Maskable 0FFD4h 42
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)
(1) (3)
DAC12_A
(4)
DAC12_0IFG, DAC12_1IFG
(1) (3)
Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG0
(3)
Maskable 0FFD0h 40
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
Timer TA2 Maskable 0FFCEh 39
TA2IFG (TA2IV)
(1) (3)
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)
(1) (3)
Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)
(1) (3)
Maskable 0FFCAh 37
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with peripheral module DAC12_A, otherwise reserved.
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