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MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333

www.ti.com

SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015

Table 4-1. Signal Descriptions (continued)

TERMINAL

NO.

I/O

(1)

DESCRIPTION

NAME

PZ

ZQW

AVSS2

15

G2

Analog ground supply

General-purpose digital I/O

P5.6/ADC12CLK/DMAE0

16

H1

I/O

Conversion clock output ADC

DMA external trigger input

General-purpose digital I/O with port interrupt and mappable secondary function

P2.0/P2MAP0

17

G4

I/O

Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

General-purpose digital I/O with port interrupt and mappable secondary function

P2.1/P2MAP1

18

H2

I/O

Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I

2

C data

General-purpose digital I/O with port interrupt and mappable secondary function

P2.2/P2MAP2

19

J1

I/O

Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I

2

C clock

General-purpose digital I/O with port interrupt and mappable secondary function

P2.3/P2MAP3

20

H4

I/O

Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

General-purpose digital I/O with port interrupt and mappable secondary function

P2.4/P2MAP4

21

J2

I/O

Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

General-purpose digital I/O with port interrupt and mappable secondary function

P2.5/P2MAP5

22

K1

I/O

Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in

General-purpose digital I/O with port interrupt and mappable secondary function

P2.6/P2MAP6

23

K2

I/O

Default mapping: no secondary function

General-purpose digital I/O with port interrupt and mappable secondary function

P2.7/P2MAP7

24

L2

I/O

Default mapping: no secondary function

DVCC1

25

L1

Digital power supply

DVSS1

26

M1

Digital ground supply

VCORE

(2)

27

M2

Regulated core power supply (internal use only, no external current loading)

P5.2

28

L3

I/O

General-purpose digital I/O

DVSS

29

M3

Digital ground supply

DNC

30

J4

Do not connect. It is strongly recommended to leave this terminal open.

P5.3

31

L4

I/O

General-purpose digital I/O

P5.4

32

M4

I/O

General-purpose digital I/O

P5.5

33

J5

I/O

General-purpose digital I/O

General-purpose digital I/O with port interrupt

P1.0/TA0CLK/ACLK

34

L5

I/O

Timer TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

P1.1/TA0.0

35

M5

I/O

Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

General-purpose digital I/O with port interrupt

P1.2/TA0.1

36

J6

I/O

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

General-purpose digital I/O with port interrupt

P1.3/TA0.2

37

H6

I/O

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

(2)

VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C

VCORE

.

Copyright © 2010–2015, Texas Instruments Incorporated

Terminal Configuration and Functions

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MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333

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Summary of Contents for MSP430F5333

Page 1: ...and 0 3 µA at 3 0 V Typical Autoscan Feature Wake up From Standby Mode in 3 µs Typical Dual 12 Bit Digital to Analog Converters DACs 16 Bit RISC Architecture Extended Memory up to With Synchronization 20 MHz System Clock Voltage Comparator Flexible Power Management System Hardware Multiplier Supports 32 Bit Operations Fully Integrated LDO With Programmable Serial Onboard Programming No External Re...

Page 2: ...r modes to active mode in 3 µs typical The MSP430F533x devices are microcontrollers with an integrated 3 3 V LDO a high performance 12 bit ADC a comparator two USCIs a hardware multiplier DMA four 16 bit timers an RTC module with alarm capabilities and up to 74 I O pins Device Information 1 PART NUMBER PACKAGE BODY SIZE 2 MSP430F5338IPZ LQFP 100 14 mm 14 mm MSP430F5338IZQW BGA 113 7 mm 7 mm 1 For ...

Page 3: ...XT2IN XT2OUT Power Management LDO SVM SVS Brownout SYS Watchdog P2 Port Mapping Controller I O Ports P3 P4 2 8 I Os Interrupt Capability PB 1 16 I Os I O Ports P5 P6 2 8 I Os PC 1 16 I Os I O Ports P7 P8 1 6 I Os PD 1 14 I Os 1 8 I Os I O Ports P9 1 8 I Os PE 1 8 I Os MPY32 TA0 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers TB0 Timer_B 7 CC Registers RTC_B Battery Backup Sys...

Page 4: ...eristics 18 5 50 LDO PWR LDO Power System 48 5 7 Schmitt Trigger Inputs General Purpose I O 19 5 51 Flash Memory 49 5 8 Inputs Ports P1 P2 P3 and P4 19 5 52 JTAG and Spy Bi Wire Interface 49 5 9 Leakage Current General Purpose I O 19 6 Detailed Description 50 5 10 Outputs General Purpose I O Full Drive 6 1 Overview 50 Strength 19 6 2 CPU 50 5 11 Outputs General Purpose I O Reduced Drive Strength 2...

Page 5: ...ditions for the Channel to channel crosstalk parameter 45 Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x axis label from fToggle to 1 fToggle in Figure 5 22 Crosstalk Test Conditions 45 Corrected the spelling of the MRG bits in the fMCLK MRG parameter 49 Removed RTC_B from LPM4 5 wake up options 52 Throughout document changed all instances of bootstrap loader to bootloader 55 ...

Page 6: ...ata symbolization and PCB design guidelines are available at www ti com packaging 3 Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available For example a number sequence of 3 5 would represent two instantiations of Timer_A the first instantiation having 3 and the second instantiation having 5 cap...

Page 7: ...6 ADC12CLK DMAE0 P5 4 P5 5 P1 0 TA0CLK ACLK P3 0 TA1CLK CBOUT P3 1 TA1 0 P3 2 TA1 1 P1 6 TA0 1 P1 7 TA0 2 P1 1 TA0 0 P1 2 TA0 1 P1 5 TA0 4 P3 3 TA1 2 P3 4 TA2CLK SMCLK P3 5 TA2 0 P3 6 TA2 1 P3 7 TA2 2 P4 0 TB0 0 P4 2 TB0 2 P4 1 TB0 1 P4 4 TB0 4 P4 3 TB0 3 P4 6 TB0 6 P4 5 TB0 5 P8 0 TB0CLK P4 7 TB0OUTH SVMOUT P8 4 UCB1CLK UCA1STE VBAK P2 1 P2MAP1 P2 2 P2MAP2 P2 3 P2MAP3 P2 4 P2MAP4 P2 5 P2MAP5 P2 6...

Page 8: ... AVSS2 P5 6 ADC12CLK DMAE0 P5 4 P5 5 P1 0 TA0CLK ACLK P3 0 TA1CLK CBOUT P3 1 TA1 0 P3 2 TA1 1 P1 6 TA0 1 P1 7 TA0 2 P1 1 TA0 0 P1 2 TA0 1 P1 5 TA0 4 P3 3 TA1 2 P3 4 TA2CLK SMCLK P3 5 TA2 0 P3 6 TA2 1 P3 7 TA2 2 P4 0 TB0 0 P4 2 TB0 2 P4 1 TB0 1 P4 4 TB0 4 P4 3 TB0 3 P4 6 TB0 6 P4 5 TB0 5 P8 0 TB0CLK P4 7 TB0OUTH SVMOUT P8 4 UCB1CLK UCA1STE VBAK P2 1 P2MAP1 P2 2 P2MAP2 P2 3 P2MAP3 P2 4 P2MAP4 P2 5 P...

Page 9: ...5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 4 3 Pin Designation MSP430F5338IZQW MSP430F5336IZQW MSP430F5335IZQW MSP430F5333IZQW Figure 4 3 shows the pin diagram for all devices in the ZQW package See Section 4 4 for pin assignments and descriptions NOTE For terminal assignments see Table 4 1 Figure 4 3 113 Pin ZQW Package Top View MSP430F5338 MSP430F5336 MSP4...

Page 10: ... input CB9 Analog input A13 ADC General purpose digital I O Comparator_B input CB10 P7 6 CB10 A14 DAC0 7 D2 I O Analog input A14 ADC DAC12 0 output not available on F5335 and F5333 devices General purpose digital I O Comparator_B input CB11 P7 7 CB11 A15 DAC1 8 D1 I O Analog input A15 ADC DAC12 1 output not available on F5335 and F5333 devices General purpose digital I O P5 0 VREF VeREF 9 D4 I O O...

Page 11: ...tal I O with port interrupt and mappable secondary function P2 6 P2MAP6 23 K2 I O Default mapping no secondary function General purpose digital I O with port interrupt and mappable secondary function P2 7 P2MAP7 24 L2 I O Default mapping no secondary function DVCC1 25 L1 Digital power supply DVSS1 26 M1 Digital ground supply VCORE 2 27 M2 Regulated core power supply internal use only no external c...

Page 12: ...t General purpose digital I O with port interrupt P3 5 TA2 0 47 M9 I O Timer TA2 capture CCR0 CCI0A CCI0B input compare Out0 output General purpose digital I O with port interrupt P3 6 TA2 1 48 L9 I O Timer TA2 capture CCR1 CCI1A CCI1B input compare Out1 output General purpose digital I O with port interrupt P3 7 TA2 2 49 M10 I O Timer TA2 capture CCR2 CCI2A CCI2B input compare Out2 output General...

Page 13: ... General purpose digital I O P8 6 UCB1SOMI UCB1SCL 66 G9 I O USCI_B1 SPI slave out master in USCI_B1 I2 C clock P8 7 67 E12 I O General purpose digital I O P9 0 68 E11 I O General purpose digital I O P9 1 69 F9 I O General purpose digital I O P9 2 70 D12 I O General purpose digital I O P9 3 71 D11 I O General purpose digital I O P9 4 72 E9 I O General purpose digital I O P9 5 73 C12 I O General pu...

Page 14: ...t clock input General purpose digital I O PJ 2 TMS 94 E7 I O Test mode select General purpose digital I O PJ 3 TCK 95 D6 I O Test clock Reset input active low 3 RST NMI SBWTDIO 96 A3 I O Nonmaskable interrupt input Spy Bi Wire data input output General purpose digital I O P6 0 CB0 A0 97 B4 I O Comparator_B input CB0 Analog input A0 ADC General purpose digital I O P6 1 CB1 A1 98 B3 I O Comparator_B...

Page 15: ...hat 500 V HBM allows safe manufacturing with a standard ESD control process Pins listed as 1000 V may actually have higher performance 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process Pins listed as 250 V may actually have higher performance 5 3 Recommended Operating Conditions MIN NOM MAX UNIT PMMCOREVx 0 1 8 3 6 Supply voltage during pro...

Page 16: ...ency maximum MCLK frequency 4 5 2 V VCC 3 6 V fSYSTEM MHz see Figure 5 1 PMMCOREVx 2 0 16 0 2 2 V VCC 3 6 V PMMCOREVx 3 0 20 0 2 4 V VCC 3 6 V 4 The MSP430 CPU is clocked directly with MCLK Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency 5 Modules may have a different maximum input clock specification See the specification of the respective...

Page 17: ...er mode 2 5 4 µA 3 V 3 6 6 7 0 11 10 12 18 0 1 6 1 8 2 4 4 7 6 5 10 5 2 2 V 1 1 6 1 9 4 8 6 6 2 1 7 2 0 4 9 6 7 Low power mode 3 ILPM3 XT1LF 0 1 9 2 1 2 7 5 0 6 8 10 8 µA crystal mode 6 4 1 1 9 2 1 5 1 7 0 3 V 2 2 0 2 2 5 2 7 1 3 2 0 2 2 2 9 5 4 7 3 12 6 1 All inputs are tied to 0 V or to VCC Outputs do not source or sink any current 2 The currents are characterized with a Micro Crystal CC4V T1A S...

Page 18: ...C 0 2 V fDCO fMCLK fSMCLK 0 MHz fACLK 32768 Hz PMMREGOFF 1 RTC in backup domain active 10 VVBAT VCC 0 2 V fDCO fMCLK fSMCLK 0 MHz fACLK 32768 Hz PMMREGOFF 1 RTC in backup domain active no current drawn on VBAK 11 fDCO fMCLK fSMCLK 0 MHz fACLK 32768 Hz PMMREGOFF 1 RTC in backup domain active no current drawn on VBAK 12 Internal regulator disabled No data retention CPUOFF 1 SCG0 1 SCG1 1 OSCOFF 1 PM...

Page 19: ...duration t int is met It may be set by trigger signals shorter than t int 5 9 Leakage Current General Purpose I O over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg Px x High impedance leakage current 1 2 1 8 V 3 V 50 nA 1 The leakage current is measured with VSS or VCC applied to the corresponding pin...

Page 20: ...o hold the maximum voltage drop specified 5 12 Output Frequency Ports P1 P2 and P3 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT VCC 1 8 V 8 PMMCOREVx 0 Port output frequency P3 4 TA2CLK SMCLK S27 fPx y MHz with load CL 20 pF RL 1 kΩ 1 or 3 2 kΩ 2 3 VCC 3 V 20 PMMCOREVx 3 VCC 1 8 V P1 0 TA0CLK ACLK S39 8 P...

Page 21: ... Level Output Voltage V OL I Typical Low Level Output Current mA OL MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 5 13 Typical Characteristics Outputs Reduced Drive Strength PxDS y 0 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted Figure 5 3 Typical Low Level Output Current vs Low Level Figu...

Page 22: ...8 V P3 2 CC V Low Level Output Voltage V OL I Typical Low Level Output Current mA OL MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 SLAS721D AUGUST 2010 REVISED DECEMBER 2015 www ti com 5 14 Typical Characteristics Outputs Full Drive Strength PxDS y 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted Figure 5 7 Typical Low Level Output Current vs ...

Page 23: ...pins XIN and XOUT Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins If conformal coating is used ensure that it does not induce capacitive resistive leakage between the oscillator pins 2 When XT1BYPASS is set XT1 circuit is automatically powered down Input signal is a digit...

Page 24: ...20 MHz 40 50 60 fFault HF Oscillator fault frequency 7 XT2BYPASS 1 8 30 300 kHz 1 Requires external capacitors at both terminals Values are specified by crystal manufacturers 2 To improve EMI on the XT2 oscillator the following guidelines should be observed Keep the traces between the device and the crystal as short as possible Design a good ground plane around the oscillator pins Prevent crosstal...

Page 25: ...FO over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT REFO oscillator current IREFO TA 25 C 1 8 V to 3 6 V 3 µA consumption REFO frequency calibrated Measured at ACLK 1 8 V to 3 6 V 32768 Hz fREFO Full temperature range 1 8 V to 3 6 V 3 5 REFO absolute tolerance calibrated TA 25 C 3 V 1 5 dfREFO dT REFO...

Page 26: ...Hz fDCO 4 0 DCO frequency 4 0 DCORSELx 4 DCOx 0 MODx 0 1 3 3 2 MHz fDCO 4 31 DCO frequency 4 31 DCORSELx 4 DCOx 31 MODx 0 12 3 28 2 MHz fDCO 5 0 DCO frequency 5 0 DCORSELx 5 DCOx 0 MODx 0 2 5 6 0 MHz fDCO 5 31 DCO frequency 5 31 DCORSELx 5 DCOx 31 MODx 0 23 7 54 1 MHz fDCO 6 0 DCO frequency 6 0 DCORSELx 6 DCOx 0 MODx 0 4 6 10 7 MHz fDCO 6 31 DCO frequency 6 31 DCORSELx 6 DCOx 31 MODx 0 39 0 88 0 M...

Page 27: ...Core voltage active VCORE3 AM 2 4 V DVCC 3 6 V 0 mA I VCORE 21 mA 1 90 V mode PMMCOREV 3 Core voltage active VCORE2 AM 2 2 V DVCC 3 6 V 0 mA I VCORE 21 mA 1 80 V mode PMMCOREV 2 Core voltage active VCORE1 AM 2 V DVCC 3 6 V 0 mA I VCORE 17 mA 1 60 V mode PMMCOREV 1 Core voltage active VCORE0 AM 1 8 V DVCC 3 6 V 0 mA I VCORE 13 mA 1 40 V mode PMMCOREV 0 Core voltage low current VCORE3 LPM 2 4 V DVCC...

Page 28: ...ower Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User s Guide SLAU208 on recommended settings and usage 5 23 PMM SVM High Side over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVMHE 0 DVCC 3 6 V 0 nA I SVMH SVMH current consumption SVMHE 1 DVCC 3 6 V SVM...

Page 29: ...ode 1 SVSLFP 1 4 MHz Wake up time from LPM2 PMMCOREV SVSMLRRL n tWAKE UP SLOW LPM3 or LPM4 to active where n 0 1 2 or 3 150 165 µs mode 2 SVSLFP 0 Wake up time from LPM3 5 or tWAKE UP LPM5 2 3 ms LPM4 5 to active mode 3 Wake up time from RST or tWAKE UP RESET 2 3 ms BOR event to active mode 3 1 This value represents the time from the wake up event to the first active edge of MCLK The wake up time ...

Page 30: ...less otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT TA 40 C 0 43 VBAT 1 7 V TA 25 C 0 52 DVCC not connected TA 60 C 0 58 RTC running TA 85 C 0 64 TA 40 C 0 50 VBAT 2 2 V TA 25 C 0 59 Current into VBAT terminal if no IVBAT DVCC not connected µA primary battery is connected TA 60 C 0 64 RTC running TA 85 C 0 71 TA 40 C 0 68 VBAT 3 V TA 25 C 0 75 DVCC not connected TA 60 C 0 79 RTC ru...

Page 31: ...nput data setup time ns 2 4 V 30 PMMCOREV 3 3 V 25 1 8 V 0 PMMCOREV 0 3 V 0 tHD MI SOMI input data hold time ns 2 4 V 0 PMMCOREV 3 3 V 0 UCLK edge to SIMO valid 1 8 V 20 CL 20 pF 3 V 18 PMMCOREV 0 tVALID MO SIMO output data valid time 2 ns 2 4 V 16 UCLK edge to SIMO valid CL 20 pF PMMCOREV 3 3 V 15 1 8 V 10 CL 20 pF PMMCOREV 0 3 V 8 tHD MO SIMO output data hold time 3 ns 2 4 V 10 CL 20 pF PMMCOREV...

Page 32: ...O HI 1 fUCxCLK MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 SLAS721D AUGUST 2010 REVISED DECEMBER 2015 www ti com Figure 5 11 SPI Master Mode CKPH 0 Figure 5 12 SPI Master Mode CKPH 1 32 Specifications Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 ...

Page 33: ... 3 V 5 tHD SI SIMO input data hold time ns 2 4 V 5 PMMCOREV 3 3 V 5 UCLK edge to SOMI valid 1 8 V 76 CL 20 pF 3 V 60 PMMCOREV 0 tVALID SO SOMI output data valid time 2 ns UCLK edge to SOMI valid 2 4 V 44 CL 20 pF 3 V 40 PMMCOREV 3 1 8 V 18 CL 20 pF PMMCOREV 0 3 V 12 tHD SO SOMI output data hold time 3 ns 2 4 V 10 CL 20 pF PMMCOREV 3 3 V 8 1 fUCxCLK 1 2tLO HI with tLO HI max tVALID MO Master tSU SI...

Page 34: ... fUCxCLK tLO HI tLO HI tSTE LAG tSTE DIS tSTE ACC tHD SO MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 SLAS721D AUGUST 2010 REVISED DECEMBER 2015 www ti com Figure 5 13 SPI Slave Mode CKPH 0 Figure 5 14 SPI Slave Mode CKPH 1 34 Specifications Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 ...

Page 35: ...0 10 fSCL SCL clock frequency 2 2 V 3 V 0 400 kHz fSCL 100 kHz 4 0 tHD STA Hold time repeated START 2 2 V 3 V µs fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU STA Setup time for a repeated START 2 2 V 3 V µs fSCL 100 kHz 0 6 tHD DAT Data hold time 2 2 V 3 V 0 ns tSU DAT Data setup time 2 2 V 3 V 250 ns fSCL 100 kHz 4 0 tSU STO Setup time for STOP 2 2 V 3 V µs fSCL 100 kHz 0 6 2 2 V 50 600 Pulse duration o...

Page 36: ...X UNIT For specified performance of ADC12 linearity parameters using an external reference voltage or 0 45 4 8 5 0 AVCC as reference 1 fADC12CLK ADC conversion clock For specified performance of ADC12 linearity 2 2 V 3 V MHz 0 45 2 4 4 0 parameters using the internal reference 2 For specified performance of ADC12 linearity 0 45 2 4 2 7 parameters using the internal reference 3 Internal ADC12 fADC1...

Page 37: ...2 LSB EG Gain error 3 See 2 2 2 V 3 V 2 4 LSB ET Total unadjusted error See 2 2 2 V 3 V 2 5 LSB 1 Parameters are derived using the histogram method 2 AVCC as reference voltage is selected by SREF2 0 SREF1 0 SREF0 0 3 Parameters are derived using a best fit curve 5 38 12 Bit ADC Linearity Parameters Using the Internal Reference Voltage over recommended ranges of supply voltage and operating free ai...

Page 38: ...selected 4 Error of conversion result 1 LSB 1 The temperature sensor is provided by the REF module See the REF module parametric IREF regarding the current consumption of the temperature sensor 2 The temperature sensor offset can be significant A single point calibration is recommended to minimize the offset error of the built in temperature sensor The TLV structure contains calibration values for...

Page 39: ...The input capacitance Ci is also the dynamic load for an external reference during conversion The dynamic impedance of the reference supply should follow the recommendations on analog source impedance to let the charge settle for 12 bit accuracy 2 The accuracy limits the minimum positive external reference voltage Lower reference voltage levels may be applied with reduced accuracy requirements 3 T...

Page 40: ...2 REFOUT 0 75 REFON 0 1 Settling time of reference tSETTLE µs AVCC AVCC min through AVCC max voltage 8 CVREF CVREF max 75 REFVSEL 0 1 2 REFOUT 1 REFON 0 1 1 The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC The ADC uses two internal buffers one smaller and one larger for driving the VREF terminal When REFOUT 1 the reference is available at the VREF termi...

Page 41: ...er recommended ranges of supply voltage and operating free air temperature unless otherwise noted see Figure 5 17 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Resolution 12 bit monotonic 12 bits VeREF 1 5 V DAC12AMPx 7 DAC12IR 1 2 2 V 2 4 2 Integral INL LSB nonlinearity 1 VeREF 2 5 V DAC12AMPx 7 DAC12IR 1 3 V 2 4 VeREF 1 5 V DAC12AMPx 7 DAC12IR 1 2 2 V 0 4 1 2 Differential DNL LSB nonlinearity 1...

Page 42: ... G dT 2 2 V 3 V 10 coefficient 1 FSR C DAC12AMPx 2 165 Time for offset tOffset_Cal DAC12AMPx 3 5 2 2 V 3 V 66 ms calibration 4 DAC12AMPx 4 6 7 16 5 4 The offset calibration can be done if DAC12AMPx 2 3 4 5 6 7 The output operational amplifier is switched off with DAC12AMPx 0 1 TI recommends configuring the DAC12 module before initiating calibration Port activity during calibration may effect accur...

Page 43: ... 0h DAC12IR 1 0 0 1 DAC12AMPx 7 RLoad 3 kΩ VeREF AVCC AVCC DAC12_xDAT 0FFFh DAC12IR 1 AVCC 0 13 DAC12AMPx 7 Maximum DAC12 CL DAC12 2 2 V 3 V 100 pF load capacitance DAC12AMPx 2 DAC12_xDAT 0FFFh 1 VO P DAC12 AVCC 0 3 Maximum DAC12 IL DAC12 2 2 V 3 V mA load current DAC12AMPx 2 DAC12_xDAT 0h 1 VO P DAC12 0 3 V RLoad 3 kΩ VO P DAC12 0 3 V 150 250 DAC12AMPx 2 DAC12_xDAT 0h Output resistance RLoad 3 kΩ...

Page 44: ...e 48 kΩ for each channel when divide is enabled Can be increased if performance can be maintained 6 When DAC12IR 1 and DAC12SREFx 0 or 1 for both channels the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance 5 46 12 Bit DAC Dynamic Specifications VREF VCC DAC12IR 1 see Figure 5 19 and Figure 5 20 over recommended ranges of supply voltage and o...

Page 45: ...P MAX UNIT DAC12AMPx 2 3 4 DAC12SREFx 2 40 DAC12IR 1 DAC12_xDAT 800h 3 dB bandwidth VDC 1 5 V DAC12AMPx 5 6 DAC12SREFx 2 BW 3dB 2 2 V 3 V 180 kHz VAC 0 1 VPP DAC12IR 1 DAC12_xDAT 800h see Figure 5 21 DAC12AMPx 7 DAC12SREFx 2 550 DAC12IR 1 DAC12_xDAT 800h DAC12_0DAT 800h No load DAC12_1DAT 80h F7Fh RLoad 3 kΩ 80 Channel to channel fDAC12_1OUT 10 kHz at 50 50 duty cycle crosstalk 1 see 2 2 V 3 V dB ...

Page 46: ...MD 01 10 10 CIN Input capacitance 5 pF ON switch closed 3 4 kΩ RSIN Series input resistance OFF switch open 50 MΩ CBPWRMD 00 CBF 0 450 ns Propagation delay tPD CBPWRMD 01 CBF 0 600 response time CBPWRMD 10 CBF 0 50 µs CBPWRMD 00 CBON 1 CBF 1 0 35 0 6 1 0 CBFDLY 00 CBPWRMD 00 CBON 1 CBF 1 0 6 1 0 1 8 CBFDLY 01 Propagation delay with tPD filter µs filter active CBPWRMD 00 CBON 1 CBF 1 1 0 1 8 3 4 CB...

Page 47: ...d operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT VLDOO 3 3 V 10 IOH 25 mA VOH High level output voltage 2 4 V See Figure 5 24 for typical characteristics VLDOO 3 3 V 10 IOL 25 mA VOL Low level output voltage 0 4 V See Figure 5 23 for typical characteristics VLDOO 3 3 V 10 VIH High level input voltage 2 0 V See Figure 5 25 for typical characteristics VL...

Page 48: ...CH LDO input detection threshold 3 75 V VLDOI LDO input voltage Normal operation 3 76 5 5 V VLDO LDO output voltage 3 3 9 V LDOO terminal input voltage with LDO VLDO_EXT LDO disabled 1 8 3 6 V disabled ILDOO Maximum external current from LDOO terminal LDO is on 20 mA IDET LDO current overload detection 1 60 100 mA CLDOI LDOI terminal recommended capacitance 4 7 µF CLDOO LDOO terminal recommended c...

Page 49: ...1 MHz FCTL4 MRG0 1 or FCTL4 MRG1 1 1 The cumulative program time must not be exceeded when writing to a 128 byte flash block This parameter applies to all programming methods individual word or byte write and block write modes 2 These values are hardwired into the flash controller state machine 5 52 JTAG and Spy Bi Wire Interface over recommended ranges of supply voltage and operating free air tem...

Page 50: ...6 2 CPU The MSP430 CPU has a 16 bit RISC architecture that is highly transparent to the application All operations other than program flow instructions are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand The CPU is integrated with 16 registers that provide reduced instruction execution time The registe...

Page 51: ...tion ADD R4 R5 R4 R5 R5 Single operands destination only CALL R8 PC TOS R8 PC Relative jump un conditional JNE Jump on equal bit 0 Table 6 2 Address Mode Descriptions ADDRESS MODE S 1 D 1 SYNTAX EXAMPLE OPERATION Register MOV Rs Rd MOV R10 R11 R10 R11 Indexed MOV X Rn Y Rm MOV 2 R5 6 R6 M 2 R5 M 6 R6 Symbolic PC relative MOV EDE TONI M EDE M TONI Absolute MOV MEM TCDAT M MEM M TCDAT Indirect MOV R...

Page 52: ... LPM2 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DC generator of the DCO remains enabled ACLK remains active Low power mode 3 LPM3 CPU is disabled MCLK FLL loop control and DCOCLK are disabled DC generator of the DCO is disabled ACLK remains active Low power mode 4 LPM4 CPU is disabled ACLK is disabled MCLK FLL loop control and DCOCLK are disabled DC generator of the DCO is disa...

Page 53: ...skable 0FFEAh 53 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4 Timer TA0 Maskable 0FFE8h 52 TA0IFG TA0IV 1 3 LDO PWR LDOOFFIG LDOONIFG LDOOVLIFG Maskable 0FFE6h 51 DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA Maskable 0FFE4h 50 DMA4IFG DMA5IFG DMAIV 1 3 Timer TA1 TA1CCR0 CCIFG0 3 Maskable 0FFE2h 49 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2 Timer TA1 Maskable 0FFE0h 48 TA1IFG TA1IV 1 3 I O Port P1 P1IFG 0 to P1IFG 7 P1IV 1 3 Mas...

Page 54: ...ctor 2 N A 4KB 4KB 0053FFh 004400h 0053FFh 004400h RAM Sector 1 4KB 4KB 4KB 0043FFh 003400h 0043FFh 003400h 0043FFh 003400h Sector 0 4KB 4KB 4KB 0033FFh 002400h 0033FFh 002400h 0033FFh 002400h Sector 7 2KB 2KB 2KB RAM 0023FFh 001C00h 0023FFh 001C00h 0023FFh 001C00h Info A 128 B 128 B 128 B 0019FFh 001980h 0019FFh 001980h 0019FFh 001980h Info B 128 B 128 B 128 B 00197Fh 001900h 00197Fh 001900h 0019...

Page 55: ... device programmers Table 6 6 lists the JTAG pin requirements For further details on interfacing to development tools and device programmers see the MSP430 Hardware Tools User s Guide SLAU278 For a complete description of the features of the JTAG interface and its implementation see MSP430 Programming Via the JTAG Interface SLAU320 Table 6 6 JTAG Pin Requirements and Functions DEVICE SIGNAL DIRECT...

Page 56: ...gle byte single word and long word writes to the flash memory Features of the flash memory include Flash memory has n segments of main memory and four segments of information memory A to D of 128 bytes each Each segment in main memory is 512 bytes in size Segments 0 to n may be erased in one step or each segment may be individually erased Segments A to D can be erased individually or as a group wi...

Page 57: ...combination of input output and interrupt conditions is possible Programmable pullup or pulldown on all ports Programmable drive strength on all ports Edge selectable interrupt input capability for all the eight bits of ports P1 P2 P3 and P4 Read and write access to port control registers is supported by all instructions Ports can be accessed byte wise P1 through P9 or word wise in pairs PA throug...

Page 58: ...ed None DVSS Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents 31 0FFh 1 PM_ANALOG when applying analog signals 1 The value of the PM_ANALOG mnemonic is set to 0FFh The port mapping registers are 5 bits wide and the upper bits are ignored which results in a maximum value of 31 Table 6 9 lists the default port mapping for all supported pins Table 6 9 Defau...

Page 59: ... the proper internal reset signal to the device during power on and power off The SVS and SVM circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision the device is automatically reset and supply voltage monitoring the device is not automatically reset SVS and SVM circuitry is available on the primary supply and core supply 6 12 5 Har...

Page 60: ...No interrupt pending 00h Brownout BOR 02h Highest RST NMI BOR 04h PMMSWBOR BOR 06h LPM3 5 or LPM4 5 wakeup BOR 08h Security violation BOR 0Ah SVSL POR 0Ch SVSH POR 0Eh SVML_OVP POR 10h SYSRSTIV System Reset 019Eh SVMH_OVP POR 12h PMMSWPOR POR 14h WDT time out PUC 16h WDT key violation PUC 18h KEYV flash key violation PUC 1Ah Reserved 1Ch Peripheral area fetch PUC 1Eh PMM key violation PUC 20h Rese...

Page 61: ...NNEL TRIGGER 0 1 2 3 4 5 0 DMAREQ 1 TA0CCR0 CCIFG 2 TA0CCR2 CCIFG 3 TA1CCR0 CCIFG 4 TA1CCR2 CCIFG 5 TA2CCR0 CCIFG 6 TA2CCR2 CCIFG 7 TBCCR0 CCIFG 8 TBCCR2 CCIFG 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 UCA0RXIFG 17 UCA0TXIFG 18 UCB0RXIFG 19 UCB0TXIFG 20 UCA1RXIFG 21 UCA1TXIFG 22 UCB1RXIFG 23 UCB1TXIFG 24 ADC12IFGx 25 DAC12_0IFG 2 26 DAC12_1IFG 2 27 Reser...

Page 62: ... timing TA0 also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each capture compare register Table 6 12 Timer TA0 Signal Connections INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 34 P1 0 L5 P1 0 TA0CLK TACLK ACLK ACLK Timer NA NA SMCL...

Page 63: ...ULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 42 P3 0 L7 P3 0 TA1CLK TACLK ACLK ACLK Timer NA NA SMCLK SMCLK 42 P3 0 L7 P3 0 TA1CLK TACLK 43 P3 1 H7 P3 1 TA1 0 CCI0A 43 P3 1 H7 P3 1 DVSS CCI0B CCR0 TA0 TA1 0 DVSS GND DVCC VCC 44 P3 2 M8 P3 2 TA1 1 CCI1A 44 P3 2 M8 P3 2 DAC12_A 1 CBOUT CCI1B DAC12_0 DAC12_1 internal CCR1 TA1 TA1 1 inte...

Page 64: ...ctions INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK PZ ZQW PZ ZQW SIGNAL SIGNAL SIGNAL SIGNAL 46 P3 4 J8 P3 4 TA2CLK TACLK ACLK ACLK Timer NA NA SMCLK SMCLK 46 P3 4 J8 P3 4 TA2CLK TACLK 47 P3 5 M9 P3 5 TA2 0 CCI0A 47 P3 5 M9 P3 5 DVSS CCI0B CCR0 TA0 TA2 0 DVSS GND DVCC VCC 48 P3 6 L9 P3 6 TA2 1 CCI1A 48 P3 6 L9 P3 6 CBOUT CCI1B internal CCR1...

Page 65: ...HSx 2 DVCC VCC 51 P4 1 M11 P4 1 TB0 1 CCI1A 51 P4 1 M11 P4 1 P2MAPx 1 P2MAPx 1 TB0 1 CCI1B P2MAPx 1 P2MAPx 1 CCR1 TB1 TB0 1 ADC12 internal DVSS GND ADC12SHSx 3 DVCC VCC 52 P4 2 L10 P4 2 TB0 2 CCI2A 52 P4 2 L10 P4 2 P2MAPx 1 P2MAPx 1 TB0 2 CCI2B P2MAPx 1 P2MAPx 1 DAC12_A 2 CCR2 TB2 TB0 2 DVSS GND DAC12_0 DAC12_1 internal DVCC VCC 53 P4 3 M12 P4 3 TB0 3 CCI3A 53 P4 3 M12 P4 3 P2MAPx 1 P2MAPx 1 TB0 3...

Page 66: ...e REF Module Link to User s Guide The REF module generates all of the critical reference voltages that can be used by the various analog peripherals in the device 6 12 20 LDO and PU Port The integrated 3 3 V power system incorporates an integrated 3 3 V LDO regulator that allows the entire MSP430 microcontroller to be powered from nominal 5 V LDOI when it is made available for the system Alternati...

Page 67: ...2Eh Timer TA1 see Table 6 34 0380h 000h 02Eh Timer TB0 see Table 6 35 03C0h 000h 02Eh Timer TA2 see Table 6 36 0400h 000h 02Eh Battery Backup see Table 6 37 0480h 000h 01Fh RTC_B see Table 6 38 04A0h 000h 01Fh 32 bit Hardware Multiplier see Table 6 39 04C0h 000h 02Fh DMA General Control see Table 6 40 0500h 000h 00Fh DMA Channel 0 see Table 6 40 0510h 000h 00Ah DMA Channel 1 see Table 6 40 0520h 0...

Page 68: ... Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 6 20 CRC16 Registers Base Address 0150h REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC result CRC16INIRES 04h Table 6 21 RAM Control Registers Base Address 0158h REGISTER DESCRIPTION REGISTER OFFSET RAM control 0 RCCTL0 00h Table 6 22 Watchdog Registers Base Address 015Ch REGISTER DESCRIPTION REGISTER OFFSET Watchdog t...

Page 69: ...N REGISTER OFFSET Port mapping password PMAPPWD 00h Port mapping control PMAPCTL 02h Port P2 0 mapping P2MAP0 00h Port P2 1 mapping P2MAP1 01h Port P2 2 mapping P2MAP2 02h Port P2 3 mapping P2MAP3 03h Port P2 4 mapping P2MAP4 04h Port P2 5 mapping P2MAP5 05h Port P2 6 mapping P2MAP6 06h Port P2 7 mapping P2MAP7 07h Table 6 27 Port P1 P2 Registers Base Address 0200h REGISTER DESCRIPTION REGISTER OF...

Page 70: ...IE 1Ah Port P3 interrupt flag P3IFG 1Ch Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup pulldown enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh Port P4 interrupt vector word P4IV 1Eh Port P4 interrupt edge select P4IES 19h Port P4 interrupt enable P4IE 1Bh Port P4 interrupt flag P4IFG 1Dh Table 6 29 Port P5 P6 Registers Base ...

Page 71: ...9DS 08h Port P9 selection P9SEL 0Ah Table 6 32 Port J Registers Base Address 0320h REGISTER DESCRIPTION REGISTER OFFSET Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup pulldown enable PJREN 06h Port PJ drive strength PJDS 08h Table 6 33 TA0 Registers Base Address 0340h REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture compare control 0 T...

Page 72: ...compare control 4 TB0CCTL4 0Ah Capture compare control 5 TB0CCTL5 0Ch Capture compare control 6 TB0CCTL6 0Eh TB0 counter TB0R 10h Capture compare 0 TB0CCR0 12h Capture compare 1 TB0CCR1 14h Capture compare 2 TB0CCR2 16h Capture compare 3 TB0CCR3 18h Capture compare 4 TB0CCR4 1Ah Capture compare 5 TB0CCR5 1Ch Capture compare 6 TB0CCR6 1Eh TB0 expansion 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh Ta...

Page 73: ...3h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary to BCD conversion BIN2BCD 1Ch BCD to binary conversion BCD2BIN 1Eh Table 6 39 32 Bit Hardware Multiplier Registers Base Address 04C0h REGISTER DESCRIPTION REGISTER OFFSET 16 bi...

Page 74: ...rol DMA module control 4 DMACTL4 08h DMA general control DMA interrupt vector DMAIV 0Ah DMA channel 0 control DMA0CTL 00h DMA channel 0 source address low DMA0SAL 02h DMA channel 0 source address high DMA0SAH 04h DMA channel 0 destination address low DMA0DAL 06h DMA channel 0 destination address high DMA0DAH 08h DMA channel 0 transfer size DMA0SZ 0Ah DMA channel 1 control DMA1CTL 00h DMA channel 1...

Page 75: ...trol 1 UCA0CTL1 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interr...

Page 76: ...1 UCB1BR1 07h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh Table 6 45 ADC12_A Registers Base Address 0700h REGISTER DESCRIPTION REGISTER OF...

Page 77: ... 13 ADC12MEM13 3Ah Conversion memory 14 ADC12MEM14 3Ch Conversion memory 15 ADC12MEM15 3Eh Table 6 46 DAC12_A Registers Base Address 0780h REGISTER DESCRIPTION REGISTER OFFSET DAC12_A channel 0 control 0 DAC12_0CTL0 00h DAC12_A channel 0 control 1 DAC12_0CTL1 02h DAC12_A channel 0 data DAC12_0DAT 04h DAC12_A channel 0 calibration control DAC12_0CALCTL 06h DAC12_A channel 0 calibration data DAC12_0...

Page 78: ...figuration Registers Base Address 0900h REGISTER DESCRIPTION REGISTER OFFSET LDO key ID LDOKEYID 00h PU port control PUCTL 04h LDO power control LDOPWRCTL 08h 78 Detailed Description Copyright 2010 2015 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 ...

Page 79: ...VCC P1REN x Pad Logic 1 P1DS x 0 Low drive 1 High drive D MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 Input Output Schematics 6 13 1 Port P1 P1 0 to P1 7 Input Output With Schmitt Trigger Figure 6 2 Port P1 P1 0 to P1 7 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 79 Submit Documentation Feedback Pr...

Page 80: ...mer TA0 1 output 1 1 P1 3 TA0 2 3 P1 3 I O I 0 O 1 0 Timer TA0 CCI2A capture input 0 1 Timer TA0 2 output 1 1 P1 4 TA0 3 4 P1 4 I O I 0 O 1 0 Timer TA0 CCI3A capture input 0 1 Timer TA0 3 output 1 1 P1 5 TA0 4 5 P1 5 I O I 0 O 1 0 Timer TA0 CCI4A capture input 0 1 Timer TA0 4 output 1 1 P1 6 TA0 1 6 P1 6 I O I 0 O 1 0 Timer TA0 CCI1B capture input 0 1 Timer TA0 1 output 1 1 P1 7 TA0 2 7 P1 7 I O I...

Page 81: ... x 1 0 DVSS DVCC P2REN x Pad Logic 1 P2DS x 0 Low drive 1 High drive D From Port Mapping MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 2 Port P2 P2 0 to P2 7 Input Output With Schmitt Trigger Figure 6 3 Port P2 P2 0 to P2 7 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 81 Submit Documentation Feedback ...

Page 82: ... 0 Mapped secondary digital function X 1 19 P2 3 P2MAP3 3 P2 3 I O I 0 O 1 0 Mapped secondary digital function X 1 19 P2 4 P2MAP4 4 P2 4 I O I 0 O 1 0 Mapped secondary digital function X 1 19 P2 5 P2MAP5 5 P2 5 I O I 0 O 1 0 Mapped secondary digital function X 1 19 P2 6 P2MAP6 6 P2 6 I O I 0 O 1 0 Mapped secondary digital function X 1 19 P2 7 P2MAP7 7 P2 7 I O I 0 O 1 0 Mapped secondary digital fu...

Page 83: ...ive D P3IRQ x Interrupt Edge Select Q EN Set P3SEL x P3IES x P3IFG x P3IE x MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 3 Port P3 P3 0 to P3 7 Input Output With Schmitt Trigger Figure 6 4 Port P3 P3 0 to P3 7 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 83 Submit Documentation Feedback Product Folde...

Page 84: ...nput 0 1 Timer TA1 1 output 1 1 P3 3 TA1 2 3 P3 3 I O I 0 O 1 0 Timer TA1 CCI2A capture input 0 1 Timer TA1 2 output 1 1 P3 4 TA2CLK SMCLK 4 P3 4 I O I 0 O 1 0 Timer TA2 TA2CLK 0 1 SMCLK 1 1 P3 5 TA2 0 5 P3 5 I O I 0 O 1 0 Timer TA2 CCI0A capture input 0 1 Timer TA2 0 output 1 1 P3 6 TA2 1 6 P3 6 I O I 0 O 1 0 Timer TA2 CCI1A capture input 0 1 Timer TA2 1 output 1 1 P3 7 TA2 2 7 P3 7 I O I 0 O 1 0...

Page 85: ...e D P4IRQ x Interrupt Edge Select Q EN Set P4SEL x P4IES x P4IFG x P4IE x MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 4 Port P4 P4 0 to P4 7 Input Output With Schmitt Trigger Figure 6 5 Port P4 P4 0 to P4 7 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 85 Submit Documentation Feedback Product Folder ...

Page 86: ... TB0 3 3 P4 3 I O I 0 O 1 0 Timer TB0 CCI3A capture input 0 1 Timer TB0 3 output 1 1 1 P4 4 TB0 4 4 P4 4 I O I 0 O 1 0 Timer TB0 CCI4A capture input 0 1 Timer TB0 4 output 1 1 1 P4 5 TB0 5 5 P4 5 I O I 0 O 1 0 Timer TB0 CCI5A capture input 0 1 Timer TB0 5 output 1 1 1 P4 6 TB0 6 6 P4 6 I O I 0 O 1 0 Timer TB0 CCI6A capture input 0 1 Timer TB0 6 output 1 1 1 P4 7 TB0OUTH 7 P4 7 I O I 0 O 1 0 SVMOUT...

Page 87: ...arasitic cross currents when applying analog signals An external voltage can be applied to VeREF and used as the reference for the ADC12_A Comparator_B or DAC12_A 4 Setting the P5SEL 0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals The ADC12_A VREF reference is available at the pin 5 Setting the P5SEL 1 bit disables the...

Page 88: ...th Schmitt Trigger Figure 6 7 Port P5 P5 2 to P5 7 Schematic Table 6 54 Port P5 P5 2 to P5 7 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P5 x x FUNCTION P5DIR x P5SEL x P5 2 2 P5 2 I O I 0 O 1 0 P5 3 3 P5 3 I O I 0 O 1 0 P5 4 4 P5 4 I O I 0 O 1 0 P5 5 5 P5 5 I O I 0 O 1 0 P5 6 ADC12CLK DMAE0 6 P5 6 I O I 0 O 1 0 ADC12CLK 1 1 DMAE0 0 1 P5 7 RTCCLK 7 P5 7 I O I 0 O 1 0 RTCCLK 1 1 88 Detailed Desc...

Page 89: ...or_B CBPD x 0 1 2 Dvss 0 if DAC12AMPx 0 1 if DAC12AMPx 1 2 if DAC12AMPx 1 DAC12AMPx 0 DAC12OPS MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 7 Port P6 P6 0 to P6 7 Input Output With Schmitt Trigger Figure 6 8 Port P6 P6 0 to P6 7 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 89 Submit Documentation Fee...

Page 90: ...B4 A4 4 P6 4 I O I 0 O 1 0 0 n a n a CB4 X X 1 n a n a A4 2 3 X 1 X n a n a P6 5 CB5 A5 5 P6 5 I O I 0 O 1 0 0 n a n a CB5 X X 1 n a n a A5 2 3 X 1 X n a n a P6 6 CB6 A6 DAC0 6 P6 6 I O I 0 O 1 0 0 X 0 CB6 X X 1 X 0 A6 2 3 X 1 X X 0 DAC0 X X X 0 1 P6 7 CB7 A7 DAC1 7 P6 7 I O I 0 O 1 0 0 X 0 CB7 X X 1 X 0 A7 2 3 X 1 X X 0 DAC1 X X X 0 1 1 X Don t care 2 Setting the P6SEL x bit disables the output d...

Page 91: ...30F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 8 Port P7 P7 2 Input Output With Schmitt Trigger Figure 6 9 Port P7 P7 2 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 91 Submit Documentation Feedback Product Folder Links MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 ...

Page 92: ...2BYPASS P7 2 XT2IN 2 P7 2 I O I 0 O 1 0 X X XT2IN crystal mode 2 X 1 X 0 XT2IN bypass mode 2 X 1 X 1 P7 3 XT2OUT 3 P7 3 I O I 0 O 1 0 0 X XT2OUT crystal mode 3 X 1 X 0 P7 3 I O 3 X 1 0 1 1 X Don t care 2 Setting P7SEL 2 causes the general purpose I O to be disabled Pending the setting of XT2BYPASS P7 2 is configured for crystal mode or bypass mode 3 Setting P7SEL 2 causes the general purpose I O t...

Page 93: ... 0 if DAC12AMPx 0 1 if DAC12AMPx 1 2 if DAC12AMPx 1 DAC12AMPx 0 DAC12OPS MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 6 13 10 Port P7 P7 4 to P7 7 Input Output With Schmitt Trigger Figure 6 11 Port P7 P7 4 to P7 7 Schematic Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 93 Submit Documentation Feedback Product Folder...

Page 94: ... 6 I O I 0 O 1 0 0 X 0 Comparator_B input CB10 X X 1 X 0 A14 2 3 X 1 X X 0 DAC12_A output DAC0 X X X 1 1 P7 7 CB11 A15 DAC1 7 P7 7 I O I 0 O 1 0 0 X 0 Comparator_B input CB11 X X 1 X 0 A15 2 3 X 1 X X 0 DAC12_A output DAC1 X X X 1 1 1 X Don t care 2 Setting the P7SEL x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 3 Th...

Page 95: ... 0 to P8 7 Pin Functions CONTROL BITS OR SIGNALS 1 PIN NAME P9 x x FUNCTION P8DIR x P8SEL x P8 0 TB0CLK 0 P8 0 I O I 0 O 1 0 Timer TB0 TB0CLK clock input 0 1 P8 1 UCB1STE UCA1CLK 1 P8 1 I O I 0 O 1 0 UCB1STE UCA1CLK X 1 P8 2 UCA1TXD UCA1SIMO 2 P8 2 I O I 0 O 1 0 UCA1TXD UCA1SIMO X 1 P8 3 UCA1RXD UCA1SOMI 3 P8 3 I O I 0 O 1 0 UCA1RXD UCA1SOMI X 1 P8 4 UCB1CLK UCA1STE 4 P8 4 I O I 0 O 1 0 UCB1CLK UC...

Page 96: ... 6 13 Port P9 P9 0 to P9 7 Schematic Table 6 59 Port P9 P9 0 to P9 7 Pin Functions CONTROL BITS OR SIGNALS PIN NAME P9 x x FUNCTION P9DIR x P9SEL x P9 0 0 P9 0 I O I 0 O 1 0 P9 1 1 P9 1 I O I 0 O 1 0 P9 2 2 P9 2 I O I 0 O 1 0 P9 3 3 P9 3 I O I 0 O 1 0 P9 4 4 P9 4 I O I 0 O 1 0 P9 5 5 P9 5 I O I 0 O 1 0 P9 6 6 P9 6 I O I 0 O 1 0 P9 7 7 P9 7 I O I 0 O 1 0 96 Detailed Description Copyright 2010 2015 ...

Page 97: ... Outputs enabled 0 1 1 0 Output high Output low Outputs enabled 0 1 1 1 Output high Output high Outputs enabled 1 0 X X Input enabled Input enabled Inputs enabled 0 0 X X Hi Z Hi Z Outputs and inputs disabled 1 PU 1 and PU 0 inputs and outputs are supplied from LDOO LDOO can be generated by the device using the integrated 3 3 V LDO when enabled LDOO can also be supplied externally when the 3 3 V L...

Page 98: ...8 MSP430F5336 MSP430F5335 MSP430F5333 SLAS721D AUGUST 2010 REVISED DECEMBER 2015 www ti com 6 13 14 Port J J 0 JTAG Pin TDO Input Output With Schmitt Trigger or Output Figure 6 15 Port J PJ 0 Schematic 6 13 15 Port J J 1 to J 3 JTAG Pins TMS TCK TDI TCLK Input Output With Schmitt Trigger or Output Figure 6 16 Port PJ PJ 1 to PJ 3 Schematic 98 Detailed Description Copyright 2010 2015 Texas Instrume...

Page 99: ...I O 2 I 0 O 1 TDI TCLK 3 4 X PJ 2 TMS 2 PJ 2 I O 2 I 0 O 1 TMS 3 4 X PJ 3 TCK 3 PJ 3 I O 2 I 0 O 1 TCK 3 4 X 1 X Don t care 2 Default condition 3 The pin direction is controlled by the JTAG module 4 In JTAG mode pullups are activated automatically on TMS TCK and TDI TCLK PJREN x are don t care Copyright 2010 2015 Texas Instruments Incorporated Detailed Description 99 Submit Documentation Feedback ...

Page 100: ... Y position 01A10h 2 per unit per unit per unit per unit Test results 01A12h 2 per unit per unit per unit per unit ADC12 calibration tag 01A14h 1 11h 11h 11h 11h ADC12 calibration length 01A15h 1 10h 10h 10h 10h ADC gain factor 01A16h 2 per unit per unit per unit per unit ADC offset 01A18h 2 per unit per unit per unit per unit ADC 1 5 V reference 01A1Ah 2 per unit per unit per unit per unit temper...

Page 101: ...feature header pin outs for prototyping Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included The following table shows the compatible target boards and the supported packages PACKAGE TARGET BOARD AND PROGRAMMER BUNDLE TARGET BOARD ONLY 100 pin LQFP PZ MSP FET430U100C MSP TS430PZ100C 7 1 1 2 2 2 Experimenter Boards Experimenter Boards and Evalua...

Page 102: ...Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all MSP430 MCU devices and support tools Each MSP430 MCU commercial family member has one of three prefixes MSP PMS or XMS for example MSP430F5438A TI recommends two of three possible prefix designators for its support tools MSP and MSPX These prefixes represent evolutionary stages of p...

Page 103: ...C to 105 C HT Extreme Temperature Parts 55 C to 150 C Q1 Automotive Q100 Qualified MSP 430 F 5 438 A I ZQW T EP Processor Family Series Optional Temperature Range MCU Platform Packaging Device Type Optional A Revision Optional Tape and Reel Feature Set Optional Additional Features MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333 www ti com SLAS721D AUGUST 2010 REVISED DECEMBER 2015 Predictions show...

Page 104: ...the functional specifications for this device SLAZ274 MSP430F5333 Device Erratasheet Describes the known exceptions to the functional specifications for this device 7 3 Related Links Table 7 1 lists quick access links Categories include technical documents support and community resources tools and software and quick access to sample or buy Table 7 1 Related Links TECHNICAL TOOLS SUPPORT PARTS PROD...

Page 105: ...o complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications 7 7 Export Control Notice Recipient agrees to not knowingly export or re export directly or indirectly any product or technical data as defined by the U S EU and other Export Administration Regulations includ...

Page 106: ...ZQWR ACTIVE BGA MICROSTAR JUNIOR ZQW 113 2500 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M430F5335 MSP430F5335IZQWT ACTIVE BGA MICROSTAR JUNIOR ZQW 113 250 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 M430F5335 MSP430F5336IPZ ACTIVE LQFP PZ 100 90 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 M430F5336 MSP430F5336IPZR ACTIVE LQFP PZ 100 1000 Green RoHS no Sb Br...

Page 107: ... RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature 4 There may be additional marking w...

Page 108: ...OSTA R JUNI OR ZQW 113 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430F5335IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430F5336IZQWR BGA MI CROSTA R JUNI OR ZQW 113 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430F5336IZQWT BGA MI CROSTA R JUNI OR ZQW 113 250 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q1 MSP430F5338IZQWR BGA MI CROSTA R JUNI ZQW 113 2500 330 0 16 4 7 3 7 ...

Page 109: ...R BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430F5335IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430F5335IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336 6 336 6 28 6 MSP430F5336IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430F5336IZQWT BGA MICROSTAR JUNIOR ZQW 113 250 336 6 336 6 28 6 MSP430F5338IZQWR BGA MICROSTAR JUNIOR ZQW 113 2500 336 6 336 6 28 6 MSP430F53...

Page 110: ......

Page 111: ...QUAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

Page 112: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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