5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Board B
Clocks
Board A
Clocks
CLOCK INTERFACE
RP1CLK SMT SMA
--Leave room for wrench--
-must be skew matched between SMA's and U10 input
-NO STUBS
Common PCIe REFCLK
SMT SMA
-Leave room for wrench
-No stubs and all "T's"
must be balanced
Zero stub between CON5/CON4
SMA and U8/U7 Crystal input,
Nets must be identical length
-U7 configured for 100MHz output
U8 is a 25MHz xtal
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U2 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-Oscillator only installed on limited board
-RPICLKP/N nets to be matched length from "T"
-R15:18, 20:23, & 25:28 must be placed close to output
JP1 Default Settings
-Install shunt between 1-2
-Oscillator output is Hi-Z
JP2 Default Settings
-Install shunt
-Oscillator output is Hi-Z
JP3 Default Settings
-Install shunt between 1-2
-Output is Hi-Z
R35 MUST be
placed close
to input pins
of U6
U1 Output is LVPECL
Resistors R20:R23
have been configured
for CML output (mod for LVDS swing)
R24 & R29 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
R30 must be across pins of U1
FULL SILK SCREENING REQUIRED
R36 & R41 are 0 ohm 0402
resistors, May need to be
changed to 0.01uF
Capacitors to AC couple
U6 Output is LVPECL
Resistors R42:R45
have been configured
for CML output
Zero stub between CON1/CON2
SMA and U2/U1 OScillator input,
Nets must be identical length
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U5 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-RPICLKP/N nets to be matched length from "T"
-R37:40, & 42:49 must be placed close to output
Pay attention to mounting requirements for all clock sources
BRD3V3
BRD3V3
BRD3V3
BRD3V3
BRD3V3
BRD3V3
BRD3V3
BRD3V3
OUT
B_TCLKA_P
4
OUT
B_TCLKA_N
4
OUT
A_PCIE_REF_CLK_P
3
OUT
A_PCIE_REF_CLK_N
3
OUT
A_TCLKA_P 3
OUT
A_TCLKA_N 3
OUT
B_TCLKB_P
4
OUT
B_TCLKB_N
4
OUT
B_PCIE_REF_CLK_P
4
OUT
B_PCIE_REF_CLK_N
4
OUT
B_DSP_RP1CLKP
4
OUT
B_DSP_RP1CLKN
4
OUT
A_DSP_RP1CLKP 3
OUT
A_DSP_RP1CLKN 3
OUT
A_TCLKB_N 3
OUT
A_TCLKB_P 3
Title
Size
Document Number
Rev
Date:
Sheet
of
<Doc>
F
LC_2-EVM_BoC-0002 - Control Interface 1
B
5
10
Tuesday, September 13, 2011
Title
Size
Document Number
Rev
Date:
Sheet
of
<Doc>
F
LC_2-EVM_BoC-0002 - Control Interface 1
B
5
10
Tuesday, September 13, 2011
Title
Size
Document Number
Rev
Date:
Sheet
of
<Doc>
F
LC_2-EVM_BoC-0002 - Control Interface 1
B
5
10
Tuesday, September 13, 2011
C1
0.01µF
R41
0
R26
150
R19
150
U1
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacr
ef
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
G
nd1
16
GP
17
R47
150
R46
150
C10
0.
1µ
F
R36
0
R27
150
C11
DNI
R14
27
JP3
HDR_1x2
1
2
R28
150
R42
75
R34
10K
R53
0
CON3
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
R44
75
JP2
HDR_1x2
1
2
CON4
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
R43
75
JP1
HDR_1x2
1
2
U2
FXO-LC73
E/D
1
NC
2
GND
3
+OUT
4
-OUT
5
Vdd
6
C3
10µF
C7
0.01µF
U6
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacr
ef
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
G
nd1
16
GP
17
U3
Ferrite
1
1
2
2
R21
75
R18
DNI
R13
10K
R40
DNI
R23
75
R16
DNI
R54
475 1%
R33
27
R32
10K
R52
20
R39
DNI
CON2
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
R38
DNI
R37
DNI
R30
100
U5
FXO-LC73
E/D
1
NC
2
GND
3
+OUT
4
-OUT
5
Vdd
6
C6
0.01µF
J2
CON4B
1
2
3
4
R24
0
R31
150
R29
0
R45
75
CON1
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
C8
0.
01µ
F
C2
0.1µF
R35
100
R20
75
C5
0.01µF
U4
Ferrite
1
1
2
2
J1
CON4B
1
2
3
4
R22
75
R15
DNI
C4
0.1µF
U7
NB3N5573
S0
1
S1
2
NC0
3
X1
4
X2
5
OE
6
GND0
7
NC1
8
iREF
9
CLK1#
10
CLK1
11
Vdd0
12
GND1
13
CLK0#
14
CLK0
15
Vdd1
16
C9
10µ
F
R17
DNI
R51
10K
R49
150
R25
150
R50
10K
R48
150
U8
Crystal
1
1
2
2