EVM Dual BoC
Revision 0.4 – preliminary
BoC - Quick Start Guide
Page 11 of
31
coupled, however they are biased. The current biasing scheme implemented is designed
to provide the appropriate swing for most TI DSP’s available today.
The following two figures illustrate the configuration for the REFCLK generation and
biasing components. If a change in the output swing is needed, remove and replace the
appropriate components carefully.
Figure 7: REFCLK Logic
Figure 8: REFCLK Biasing Components
C18
0.1µF
C19
0.01µF
U13, C18:C19 MUST be
placed close to U3
R85:R86 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
R85
0
R86
0
R84 must be across pins of U12
R
80
1
50
R
81
1
50
R
82
1
50
R
83
1
50
OUT
A_REFCLK_P 3
OUT
B_REFCLK_P 4
OUT
A_REFCLK_N 3
OUT
B_REFCLK_N 4
NO STUBS
BRD3V3
JP10
HDR_1x2
1
2
R
76
1
0K
0.100" Header
1 shunt needed
J5 Default is Not Installed
0 = Power Down (Hi-Z)
1 = Normal (Active Output)
R75
75
R69
27
R77
75
R78
75
BRD3V3
C12
0.01µF
R79
75
R70
150
R
71
DNI
R
72
DNI
R
73
DNI
R
74
DNI
U14
FXO-LC73
E/D
1
NC
2
GND
3
+OUT
4
-OUT
5
Vdd
6
U12
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vc
c
5
INP
6
INN
7
V
ac
re
f
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
1
3
NC4
1
4
NC5
1
5
G
nd
1
1
6
GP
1
7
R84
100
U12 Output is LVPECL Resistors R71:R75 & R77:R83
have been configured for CML output.
-Resistors will need to be changed to accommodate a different swing.
-All resistors to go close to U12
U13
Ferrite
1
1
2
2
C20
0.1µF
C
17
1
0µ
F
R
8
0
1
50
R
8
1
1
50
R
8
2
1
50
R
8
3
1
50
OUT
A_REFCLK_P 3
OUT
B_REFCLK_P 4
OUT
A_REFCLK_N 3
OUT
B_REFCLK_N 4
NO STUBS
R75
75
R77
75
R78
75
BRD3V3
R79
75
R
7
1
DNI
R
7
2
DNI
R
7
3
DNI
R
7
4
DNI
U12
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacref
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
Gnd1
16
GP
17
R84
100
C20
0.1µF