EVM Dual BoC
BoC - Quick Start Guide
Revision 0.4 – preliminary
Page
16 of 31
The following two figures illustrate the configuration for the REFCLK generation and
biasing components. If a change in the output swing is needed, remove and replace the
appropriate components carefully.
Figure 12: TCLK_B Logic
Figure 13: TCLK_B Biasing Components
c. TCLK_A Signal Outputs [2, 13]
Headers J1 & J2 are provided as a means of connecting the on board clock source to
each respective DSP. TCLK_A is additionally provided on pins 1 & 2 of each header and
routed to the respective pins on the AMC connectors. There is no logic attached to these
pins which can be used to connect an alternate clock source into the DSP.
JP2 Default Settings
-Install shunt
-Oscillator output is Hi-Z
R31
150
C7
0.01µF
OUT
B_TCLKA_P
4
OUT
B_TCLKA_N
4
R33
27
JP2
HDR_1x2
1
2
R36 & R41 are 0 ohm 0402
resistors, May need to be
changed to 0.01uF
Capacitors to AC couple
U6 Output is LVPECL
Resistors R42:R45
have been configured
for CML output
C
10
0
.1
µ
F
C8
0
.0
1µ
F
J1
CON4B
1
2
3
4
BRD3V3
C9
1
0µ
F
U6
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacref
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
Gnd1
16
GP
17
BRD3V3
R34
10K
R32
10K
R36
0
R41
0
R
46
1
50
R
47
1
50
R
48
1
50
R
49
1
50
R
37
DNI
R
38
DNI
R
39
DNI
R
40
DNI
U4
Ferrite
1
1
2
2
OUT
B_TCLKB_P
4
OUT
B_TCLKB_N
4
R42
75
R35
100
R43
75
R44
75
R45
75
U5
FXO-LC73
E/D
1
NC
2
GND
3
+OUT
4
-OUT
5
Vdd
6
C6
0.01µF
R35 MUST be
placed close
to input pins
of U6
J2
CON4B
1
2
3
4
OUT
A_TCLKB_N
3
OUT
A_TCLKB_P
3
OUT
A_TCLKA_P
3
OUT
A_TCLKA_N
3
L
ed
J1
ON4B
U6
CDCLVP1102
6
I
7
Vac
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC
13
N
14151
BRD3V3
R34
10K
R
46
1
50
R
47
1
50
R
48
1
50
R
49
1
50
R
37
DNI
R
38
DNI
R
39
DNI
R
40
DNI
R42
75
R43
75
R44
75
R45
75
C6
0.01µF
R35 MUST be
placed close
to input pins
of U6
J2
4B