EVM Dual BoC
BoC - Quick Start Guide
Revision 0.4 – preliminary
Page
8 of 31
V.
Emulation Interface [1]
Your BoC contains a traditional Texas Instruments 60-pin emulation header (item 1). It
should be noted that emulation voltages across the AMCC backplane are intended for
3.3Vdc. Your BoC has been designed so that the emulation interface is also 3.3V, before
using this interface it will be necessary to confirm that your EVM’s can accommodate a
3.3V logic level without damage occurring.
The emulation interface of you BoC is daisy-chained. This means that the test data in and
test data out pins are configured such that both boards are in the scan chan at all times. If
you require separate control, use separate emulators directly connected to each
respective EVM.
VI.
SGMII Interface
Your BoC in designed to support two (2) lanes of SGMII. The SGMII interface is
connected between each board (A & B) in a manner that provides intercommunication.
Board A transmit (TX) lanes 1:0 are routed to the receive (RX) lanes 1:0 of Board B, and
Board A receive (RX) lanes 1:0 are routed to the transmit (TX) lanes 1:0 of Board B.
There are no AC coupling capacitors on your BoC, it is assume that your EVM hardware
has been properly designed and contains the appropriate AC coupling capacitors on the
respective AC nets.
VII.
PCIE Interface
Your BoC in designed to support four (4) lanes of PCIe. The PCIe interface is connected
between each board (A & B) in a manner that provides intercommunication. Board A
transmit (TX) lanes 7:4 are routed to the receive (RX) lanes 7:4 of Board B, and Board A
receive (RX) lanes 7:4 are routed to the transmit (TX) lanes 7:4 of Board B. There are no
AC coupling capacitors on your BoC, it is assume that your EVM hardware has been
properly designed and contains the appropriate AC coupling capacitors on the respective
AC nets.
In some cases a common or alternate PCIe clock may be required, where needed the
BoC has the ability to provide a common PCIe REFCLK, refer to section XVI for details
and configuration options.
WARNING
: The Emulation Interface is intended to operate at 3.3V, Confirm
that your EVM level shifts this into to correct DSP range before using this
interface
CAUTION
: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.
CAUTION
: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.