Texas Instruments CI2EVM BoC Quick Start Manual Download Page 31 | Manualshive

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Texas Instruments CI2EVM BoC Quick Start Manual Download Page 31

EVM Dual BoC

BoC - Quick Start Guide

Revision 0.4 – preliminary

Page

26 of 31

Board

Signal

Board

Signal

Board A \ 96

SRIO2_TXn

Board B \ 93

SRIO2_RXn

Board A \ 94

SRIO2_RXp

Board B \ 97

SRIO2_TXp

Board A \ 93

SRIO2_RXn

Board B \ 96

SRIO2_TXn

Board A \ 91

SRIO1_TXp

Board B \ 88

SRIO1_RXp

Board A \ 90

SRIO1_TXn

Board B \ 87

SRIO1_RXn

Board A \ 88

SRIO1_RXp

Board B \ 91

SRIO1_TXp

Board A \ 87

SRIO1_RXn

Board B \ 90

SRIO1_TXn

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Summary of Contents for CI2EVM BoC

Page 1: ...cription 3 II Hardware Configuration 6 I Initial Installation Procedure 6 II Default Jumper and Pin Settings 6 III BoC Logic Power Source Selection 20 6 IV EVM Power Source 16 17 18 7 V Emulation Inte...

Page 2: ...P 5 IN A_TCLKB_N 5 IN A_PCIE_REF_CLK_P 5 IN A_PCIE_REF_CLK_N 5 IN A_ IN A_ IN A_ IN A_ IN B_AMCC_P18_AIF5_TXN 4 IN B_AMCC_P18_AIF5_TXP 4 OUT A_AMCC_P17_AIF4_TXP 4 OUT A_AMCC_P17_AIF4_TXN 4 IN B_AMCC_P...

Page 3: ...5_PCIe_TX2N 3 IN A_AMCC_P4_PCIe_TX1P 3 IN A_AMCC_P4_PCIe_TX1N 3 IN B_PCIE_REF_CLK_P 5 IN B_PCIE_REF_CLK_N 5 IN B_TCLKA_P 5 IN B_TCLKA_N 5 IN B_TCLKB_P 5 IN B_TCLKB_N 5 IN A_AMCC_P18_AIF5 IN A_AMCC_P18...

Page 4: ...XO LC By default leave Disabled RPICLKP N nets to be matched length fro R37 40 42 49 must be placed close to o Pay attention to mounting require BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3...

Page 5: ...istor junctions to AMC headers must be identical Placement of JP6 JP8 should be identical to JP7 JP9 Placement of R67 should be identical in distance to R68 from Headers and switch BRD3V3 BRD3V3 BRD3V...

Page 6: ...LK_N 4 Title Size Date B Title Size Date B Title Size Date B R82 150 BJ_MH1 Banana 2142 1 1 F1 Fuse 0154001 01 1 2 2 MH3 Mounting_Hole 1 1 R79 75 R83 150 R74 DNI BJ_MH2 Banana 2142 1 1 C18 0 1 F F2 Fu...

Page 7: ...7 REFCLK Logic 11 Figure 8 REFCLK Biasing Components 11 Figure 9 RP1CLK Logic 13 Figure 10 RP1CLK Biasing Components 14 Figure 11 TCLK_B Interface 15 Figure 12 TCLK_B Logic 16 Figure 13 TCLK_B Biasin...

Page 8: ...on Interface J7 2 Board B TCKA B Header J1 3 Board B AMC B EVM Interface Connector 4 Auxilluary PCIe Clock Input SMA Connectors CON3 CON4 5 Board A EEPROM Address Configuration Switch J4 6 Timer Sync...

Page 9: ...na Jack BJ MH1 19 Board A B REFCLK Source Input Clock Oscillator Enable Control JP10 20 Primary BoC Power Selection Switch J6 21 Board A AMC B EVM Interface Connector 22 Board B Timer0 Output Interfac...

Page 10: ...LK SRIO TX Lane 4 1 SRIO RX Lane 4 1 TIMERIN_0 TIMEROUT_0 PHYSYNC RADSYNC REFCLKP N RP1FBP N RPICLK P N SGMII RX Lane 1 0 SGMII TX Lane 1 0 PCIe RX Lane 3 0 PCIe TX Lane 3 0 TCLK A P N TCLK B P N PCIe...

Page 11: ...Switch 0x111110 J6 20 1X3 Header Shunt Installed 1 2 JP1 8 1X2 Header Shunt Installed JP2 14 1X2 Header Shunt Installed JP3 25 1X2 Header Shunt Installed JP4 9 1X2 Header N A JP5 11 1X2 Header N A JP...

Page 12: ...tured by Pomona part numbers 1581 2 Red 2 required 17 18 1581 0 Black 1 required 16 The mounting pads on the BoC are electrically conductive Due to the height limitations and the need to clear any sup...

Page 13: ...acitors on your BoC it is assume that your EVM hardware has been properly designed and contains the appropriate AC coupling capacitors on the respective AC nets VII PCIE Interface Your BoC in designed...

Page 14: ...us for each EVM Each EEPROM is isolated from the other and resides on the AMCC backplane bus to the respective EVM From the factory this interface to each respective EVM is electrically ready for use...

Page 15: ...cillator Enable Header 19 The following table defines the possible configurations for JP10 JP10 is used to enable or disable the 30 72MHz differential clock source U14 input to the CDCLVP1102 which is...

Page 16: ...NO STUBS BRD3V3 JP10 HDR_1x2 1 2 R76 10K 0 100 Header 1 shunt needed J5 Default is Not Installed 0 Power Down Hi Z 1 Normal Active Output R75 75 R69 27 R77 75 R78 75 BRD3V3 C12 0 01 F R79 75 R70 150 R...

Page 17: ...oard B and header JP7 24 is connected to Board A This timer input pin to each respective DSP is provided for convience in the event future connection is required XIV Common RP1CLK Source Your BoC has...

Page 18: ...5 INP 6 INN 7 Vacref 8 OUTP0 9 OUTN0 10 OUTP1 11 OUTN1 12 NC3 13 NC4 14 NC5 15 Gnd1 16 GP 17 JP1 Default Settings Install shunt between 1 2 Oscillator output is Hi Z Zero stub between CON1 CON2 SMA a...

Page 19: ...e Not all EVM s directly support this feature future EVM s will incorporate this feature to allow for advanced clocking and test The clock routing is skew matched between AMC headers to within 5ps a T...

Page 20: ...ons J2 1 TCLKA_P TCLKA_N TCLKB_P TCLKB_N 4 2 3 J1 1 TCLKA_P TCLKA_N TCLKB_N TCLKB_P 4 2 3 Figure 11 TCLK_B Interface The oscillator source U5 is routed into the low jitter 1 2 clock buffer U6 the outp...

Page 21: ...R33 27 JP2 HDR_1x2 1 2 R36 R41 are 0 ohm 0402 resistors May need to be changed to 0 01uF Capacitors to AC couple U6 Output is LVPECL Resistors R42 R45 have been configured for CML output C10 0 1 F C8...

Page 22: ...differential oscillator on the BoC By default the shunt is applied on this header and the output disabled Not all EVM s directly support this feature future EVM s will incorporate this feature to all...

Page 23: ...other making use of the PHYSYNC or RADSYNC pins On future EVM s the timer pins will be routed to the AMC backplane interface until this is implemented the trigger event must be rerouted to the switch...

Page 24: ...s Triggering Switch JP7 HDR_1x1 1 R67 0 Placement of JP6 JP8 should be identical to JP7 JP9 Placement of R67 should be identical in distance to R68 from Headers and switch R68 0 FACTORYJ9 SETTINGS 01...

Page 25: ...gs and cautions must be followed to ensure proper operation XX Pin Assignment Board A The following table is provided relative to the AMC piout assignment for your BoC card Table 8 AMC B Header Pin As...

Page 26: ...Board A 41 N C Board A 130 AIF3_RXp Board A 42 12V Power Board A 129 AIF3_RXn Board A 43 GND Board A 128 GND Board A 44 PCIe4_TXp Board A 127 AIF2_TXp Board A 45 PCIe4_TXn Board A 126 AIF2_TXn Board A...

Page 27: ...eader Pin Number Signal Header Pin Number Signal Board B 1 GND Board B 170 GND Board B 2 12V Power Board B 169 TDO_2_TDI Board B 3 N C Board B 168 TDO Board B 4 N C Board B 167 TRST Board B 5 N C Boar...

Page 28: ...Board B 52 GND Board B 119 GND Board B 53 PCIe5_RXp Board B 118 AIF1_RXp Board B 54 PCIe5_RXn Board B 117 AIF1_RXn Board B 55 GND Board B 116 GND Board B 56 N C Board B 115 AIF0_TXp Board B 57 12V Pow...

Page 29: ...Xp Board B 23 SGMII1_RXp Board A 21 SGMII1_TXn Board B 24 SGMII1_RXn Board A 23 SGMII1_RXp Board B 20 SGMII1_TXp Board A 24 SGMII1_RXn Board B 21 SGMII1_TXn Board Signal Board Signal Board A 44 PCIe4_...

Page 30: ...Board B 123 AIF2_RXn Board A 124 AIF2_RXp Board B 127 AIF2_TXp Board A 123 AIF2_RXn Board B 126 AIF2_TXn Board A 121 AIF1_TXp Board B 118 AIF1_RXp Board A 120 AIF1_TXn Board B 117 AIF1_RXn Board A 11...

Page 31: ...al Board A 96 SRIO2_TXn Board B 93 SRIO2_RXn Board A 94 SRIO2_RXp Board B 97 SRIO2_TXp Board A 93 SRIO2_RXn Board B 96 SRIO2_TXn Board A 91 SRIO1_TXp Board B 88 SRIO1_RXp Board A 90 SRIO1_TXn Board B...

Page 32: ...P 5 IN A_TCLKB_N 5 IN A_PCIE_REF_CLK_P 5 IN A_PCIE_REF_CLK_N 5 IN A_ IN A_ IN A_ IN A_ IN B_AMCC_P18_AIF5_TXN 4 IN B_AMCC_P18_AIF5_TXP 4 OUT A_AMCC_P17_AIF4_TXP 4 OUT A_AMCC_P17_AIF4_TXN 4 IN B_AMCC_P...

Page 33: ...5_PCIe_TX2N 3 IN A_AMCC_P4_PCIe_TX1P 3 IN A_AMCC_P4_PCIe_TX1N 3 IN B_PCIE_REF_CLK_P 5 IN B_PCIE_REF_CLK_N 5 IN B_TCLKA_P 5 IN B_TCLKA_N 5 IN B_TCLKB_P 5 IN B_TCLKB_N 5 IN A_AMCC_P18_AIF5 IN A_AMCC_P18...

Page 34: ...XO LC By default leave Disabled RPICLKP N nets to be matched length fro R37 40 42 49 must be placed close to o Pay attention to mounting require BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3 BRD3V3...

Page 35: ...istor junctions to AMC headers must be identical Placement of JP6 JP8 should be identical to JP7 JP9 Placement of R67 should be identical in distance to R68 from Headers and switch BRD3V3 BRD3V3 BRD3V...

Page 36: ...LK_N 4 Title Size Date B Title Size Date B Title Size Date B R82 150 BJ_MH1 Banana 2142 1 1 F1 Fuse 0154001 01 1 2 2 MH3 Mounting_Hole 1 1 R79 75 R83 150 R74 DNI BJ_MH2 Banana 2142 1 1 C18 0 1 F F2 Fu...

Page 37: ...118777 HMC723LP3E MAX9979EVKIT MAX5432EVKIT MAX3397EEVKIT MAX14611EVKIT MAX4951AEEVKIT MAX9647EVKIT MAX9684EVKIT MAX4952AEVKIT MAX13035EEVKIT DS1964SEVKIT ESD EVM 001 EVAL CN0414 ARDZ K2 LTCC WBZ K1 D...

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