EVM Dual BoC
BoC - Quick Start Guide
Revision 0.4 – preliminary
Page
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XII.
Timer0 Output Headers [12, 22]
The BoC incorporates a separate single header connected (through the AMC B+
connector) to each EVM’s DSP’s Timer0 output pin [
DSP Timer0_output
BoC
Timer0_output
]. Header JP8 [22] is connected to Board B and header JP9 [12] is
connected to Board A. This timer pin can be used to initiate a trigger event which is
configurable using J5. Refer to section XVIII for additional configuration details.
Your BoC is also provided with a custom 12”-14” (30.48cm – 35.46cm) jumper wire that
can be used to connect between older EVM’s auxillary header containing the TimerOut0
pin to the either JP8 or JP9. This jumper is specifically designed with a 0.018” (0.457mm)
male pin (on one side) that if used can be inserted into the appropriate location on the
EVM auxillary header of you EVM, the opposite end contains a female header that is
designed to attach to either JP8 or JP9. Refer to section XVIII for detailed information on
configurations options.
XIII.
Timer0 Input Header [10, 24]
The BoC incorporates a separate single header connected (through the AMC B+
connector) to each EVM’s DSP’s Timer0 input pin [
DSP Timer0_input
BoC Timer0_input
].
Header JP6 [10] is connected to Board B and header JP7 [24] is connected to Board A.
This timer input pin to each respective DSP is provided for convience in the event future
connection is required.
XIV.
Common RP1CLK Source
Your BoC has the capability of supplying a common RP1CLK both EVM’s. This common
RP1CLK is generated on the BoC and sourced from a dedicated differential oscillator
through a high performance 1:2 low clock jitter buffer (U1). On your BoC is JP1, this
header and shunt are used to enable or disable the differential oscillator on the BoC. By
default the shunt is applied on this header, placing the oscillator input to the clock mux in
a Hi-Z state.
Not all EVM’s directly support this feature, future EVM’s will incorporate this feature to
allow for design debug, expandability and test. The clock routing is skew matched
between AMC headers to within 5ps.
a. RP1CLK Oscillator Enable Header [8]
The following table defines the possible configurations for JP1. JP1 is used to enable or
disable the 30.72MHz differential clock source (U2) input to the CDCLVP1102 which is
intended to provide a common clock source to both EVM’s for the RP1CLK. By default the
shunt is installed and the RP1CLK source is disabled.
CAUTION
: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.
CAUTION
: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.
