Texas Instruments CI2EVM BoC, Quick Start Manual, Page: 10 / 37

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 5 of
31
The following is a high level block diagram denoting the connectivity and functionality of the dual EVM
BoC card.
SGMII TX Lane 1:0
SGMII RX Lane 1:0
PCIe TX Lane 3:0
PCIe RX Lane 3:0
TCLK A P/N
TCLK B P/N
PCIe REFCLK P/N
I2C SDA/SCL
AIF TX Lane 5:0
AIF RX Lane 5:0
TDI
TDO
TRST#
TMS
TCLK
SRIO TX Lane 4:1
SRIO RX Lane 4:1
TIMERIN_0
TIMEROUT_0
PHYSYNC
RADSYNC
REFCLKP/N
RP1FBP/N
RPICLK P/N
SGMII RX Lane 1:0
SGMII TX Lane 1:0
PCIe RX Lane 3:0
PCIe TX Lane 3:0
TCLK A P/N
TCLK B P/N
PCIe REFCLK P/N
I2C SDA/SCL
AIF RX Lane 5:0
AIF TX Lane 5:0
TDO
TDI
TRST#
TMS
TCLK
SRIO RX Lane 4:1
SRIO TX Lane 4:1
TIMERIN_0
TIMEROUT_0
PHYSYNC
RADSYNC
REFCLKP/N
RP1FBP/N
RPICLK P/N
AMC HEADER
BOARD B
+ RP1CLK -
+ RP1FB - + PCICLK -
12Vin
à
3.3V Out
12V DC
TDO TDI TRST
#
TMS TCLK TVD
CDCLVP
OSC
CDCLVP
OSC
NB3N55
73
eeprom
eeprom
OSC
CDCLVP
OSC
12V DC
Figure 3 - Block Diagram