EVM Dual BoC
BoC - Quick Start Guide
Revision 0.4 – preliminary
Page
18 of 31
b. PCIeREFCLK Logic
The following figure illustrates the support logic for the PCIeREFCLK gerneration circuit
Figure 15: RP1CLK Logic
c. Alternate PCIeREFCLK Inputs [4]
Your BoC has been designed with auxillary SMA input connectors (CON3 & CON4) in the
event a different PCIeREFCLK frequency is desired. Should you elect to utilize this input
it will be necessary to confirm that it meets the input requirements of the crystal-to-HCSL
logic and that the corresponding outputs are properly biased, and that the crystal is
removed.
XVII.
RP1FB Source [7]
In order to sync the RP1 clock with the RP1 frame bust interfaces to each EVM, your BoC
has been designed with a direct interface. Provided are SMA connectors labeled as
CON5 and CON6. Should you elect to utilize this RP1FB input it will be necessary to
confirm that the signal provided meets the input requirements of the DSP and that the
polarities are correct. CON5 is the negative polarity input; CON6 is the positive polarity
input.
XVIII.
RADSYNC & PHYSYNC Triggering [6]
Your BoC has the ability to source a trigger and redirect it to an input on one or both
DSP’s through the AMC header. The intention of this interface is to accept a timer event
(trigger) from one EVM and redirect it to another making use of the PHYSYNC or
RADSYNC pins. On future EVM’s the timer pins will be routed to the AMC backplane
interface, until this is implemented the trigger event must be rerouted to the switch using
the jumper wire provided (as described in section XII).
Switch J5 has been included in the BoC allowing the ability to select from either DSP
Timer0out signal and through various switch configurations redirecting it to either
RADSYNC or PHYSYNC pin through the BoC AMC connector. The following figure
illustrates the basic naming conventions assigned to the switch (J5).
R50
10K
OUT
A_PCIE_REF_CLK_P 3
OUT
A_PCIE_REF_CLK_N 3
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U5 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-RPICLKP/N nets to be matched length from "T"
-R37:40, & 42:49 must be placed close to output
Pay attention to mounting requirements for all clock sources
OUT
B_PCIE_REF_CLK_P 3
OUT
B_PCIE_REF_CLK_N 3
R54
475 1%
JP3
HDR_1x2
1
2
U7
NB3N5573
S0
1
S1
2
NC0
3
X1
4
X2
5
OE
6
GND0
7
NC1
8
iREF
9
CLK1#
10
CLK1
11
Vdd0
12
GND1
13
CLK0#
14
CLK0
15
Vdd1
16
Common PCIe REFCLK
SMT SMA
-Leave room for wrench
-No stubs and all "T's"
must be balanced
Zero stub between CON5/CON4
SMA and U8/U7 Crystal input,
Nets must be identical length
-U7 configured for 100MHz output
U8 is a 25MHz xtal
U8
Cry stal
1
1
2
2
C
11
DNI
R53
0
JP3 Default Settings
-Install shunt between 1-2
-Output is Hi-Z
CON4
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
CON3
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
R51
10K
R52
20
BRD3V3
BRD3V3