EVM Dual BoC
BoC - Quick Start Guide
Revision 0.4 – preliminary
Page
14 of 31
Figure 10: RP1CLK Biasing Components
c. Alternate RP1CLK Inputs [15]
Your BoC has been designed with auxillary SMA input connectors (CON1 & CON2) in the
event a different RP1CLK frequency is desired. Should you elect to utilize this input it will
be necessary to confirm that it meets the input requirements of the CDCLVP1102 and
that the corresponding outputs are properly biased, and that the oscillator is disabled
(install JP1 shunt). CON1 is the negative polarity differential input; CON2 is the positive
polarity differential input to the CDCLVP1102.
XV.
Common TCLK_B Source
Your BoC has the capability of supplying a common TCLK_B to both EVM’s. This
common TCLK_B is generated on the BoC and sourced from a dedicated differential
oscillator through a high performance 1:2 low clock jitter buffer (U6). On your BoC is JP2;
this header and shunt are used to enable or disable the differential oscillator on the BoC.
By default the shunt is applied on this header, placing the oscillator input to the clock mux
in a Hi-Z state.
Not all EVM’s directly support this feature, future EVM’s will incorporate this feature to
allow for advanced clocking and test. The clock routing is skew matched between AMC
headers to within 5ps.
a. TCLK_B Oscillator Enable Header [14]
The AMC standard allows for external clock sources across the backplane bus, TCLK_x
are several of the clocks allowed. The following table defines the possible configurations
for JP2. JP2 is used to enable or disable the 30.72MHz differential clock source (U6)
input to the CDCLVP1102 which is intended to provide a common clock source of
U1
CDCLVP1102
0
Vcc
INP
6
INN
7
Vacref
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
Gnd1
P
Zero stub between CON1/CON2
SMA and U2/U1 OScillator input,
Nets must be identical length
CON1
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
CON2
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
CL
red
od for LVDS swing)
RP1CLK SMT SMA
--Leave room for wrench--
-must be skew matched between SMA's
and U10 input
-NO STUBS
OUT
A_DSP_RP1CLKP 3
OUT
A_DSP_RP1CLKN 3
C2
0.1µF
R20
75
R21
75
R22
75
R23
75
OUT
B_DSP_RP1CLKP 3
OUT
B_DSP_RP1CLKN 3
R
1
8
DNI
R
1
5
DNI
R
1
6
DNI
R
1
7
DNI
R
2
8
1
50
R
2
7
1
50
R
2
6
1
50
R
2
5
1
50
R30
100
BRD3V3
CAUTION
: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.