EVM Dual BoC
Revision 0.4 – preliminary
BoC - Quick Start Guide
Page 13 of
31
Table 4: JP1 RP1CLK Enable Header
JP1
ON
Disabled
OFF
Enabled
OFF
ON
1
X
2
X
b. RP1CLK Signal Levels
The output of the low jitter 1:2 clock buffer is LVPECL (low voltage PECL). As such this
logic level may not be adequate for your DSP. Consult your DSP data manual and the
data manual for the CDCLVP1102 before using this hardware. Prior to proceeding it will
also be necessary to confirm that the EVM clock source input (that the REFCLK is
connecting to) is AC coupled and/or biased. Your BoC RP1CLKp/n outputs are
not
AC
coupled, however they are biased. The current biasing scheme implemented is designed
to provide the appropriate swing for most TI DSP’s available today.
The following two figures illustrate the configuration for the REFCLK generation and
biasing components. If a change in the output swing is needed, remove and replace the
appropriate components carefully.
Figure 9: RP1CLK Logic
R13
10K
U1
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacref
8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
Gnd1
16
GP
17
JP1 Default Settings
-Install shunt between 1-2
-Oscillator output is Hi-Z
Zero stub between CON1/CON2
SMA and U2/U1 OScillator input,
Nets must be identical length
CON1
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
CON2
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
U1 Output is LVPECL
Resistors R20:R23
have been configured
for CML output (mod for LVDS swing)
RP1CLK SMT SMA
--Leave room for wrench--
-must be skew matched between SMA's
and U10 input
-NO STUBS
OUT
A_DSP_RP1CLKP 3
OUT
A_DSP_RP1CLKN 3
C2
0.1µF
R20
75
R21
75
R22
75
R23
75
C1
0.01µF
OUT
B_DSP_RP1CLKP 3
OUT
B_DSP_RP1CLKN 3
BRD3V3
R14
27
U3
Ferrite
1
1
2
2
C4
0.1µF
C5
0.01µF
R19
150
BRD3V3
C3
10µF
U2
FXO-LC73
E/D
1
NC
2
GND
3
+OUT
4
-OUT
5
Vdd
6
R
1
8
DNI
R
1
5
DNI
R
1
6
DNI
R
1
7
DNI
R
2
8
1
50
R
2
7
1
50
R
2
6
1
50
R
2
5
1
50
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U2 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-Oscillator only installed on limited board
-RPICLKP/N nets to be matched length from "T"
-R15:18, 20:23, & 25:28 must be placed close to output
R24 & R29 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
R24
0
R30
100
R29
0
BRD3V3
JP1
HDR_1x2
1
2