CS
SCLK
SDI
SDO
DAISY
ADS8684
ADS8688
DGND
CS
SCLK
SDO
SDI
H
o
s
t
C
o
n
tr
o
lle
r
RST / PD
RST / PD
SBAS582C – JULY 2014 – REVISED APRIL 2015
8.4 Device Functional Modes
8.4.1 Device Interface
8.4.1.1 Digital Pin Description
The digital data interface for the ADS8684 and ADS8688 is illustrated in
Figure 70. Pin Configuration for the Digital Interface
The signals shown in
are summarized as follows:
8.4.1.1.1
CS (Input)
CS indicates an active-low, chip-select signal. CS is also used as a control signal to trigger a conversion on the
falling edge. Each data frame begins with the falling edge of the CS signal. The analog input channel to be
converted during a particular frame is selected in the previous frame. On the CS falling edge, the devices sample
the input signal from the selected channel and a conversion is initiated using the internal clock. The device
settings for the next data frame can be input during this conversion process. When the CS signal is high, the
ADC is considered to be in an idle state.
8.4.1.1.2
SCLK (Input)
This pin indicates the external clock input for the data interface. All synchronous accesses to the device are
timed with respect to the falling edges of the SCLK signal.
8.4.1.1.3
SDI (Input)
SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for
device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line
are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made
to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of
the CS signal.
8.4.1.1.4
SDO (Output)
SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data
output frame varies depending on the register setting for the SDO format; see
. A low level on CS
releases the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the
output data stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits
on every falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z
state when CS goes high.
32
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links:
