40
60
80
100
120
140
100
1000
10000
100000
1000000
10000000
P
o
w
e
r
S
u
p
p
ly
Reje
ctio
n
Rat
io
Input Frequency (Hz)
C046
-----
± 2.5*V
REF
----- ± 1.25*V
REF
----- ± 0.625*V
REF
------ +2.5*V
REF
------+1.25*V
REF
40
60
80
100
120
140
50
500
5000
50000
500000
5000000
P
o
w
e
r
S
u
p
p
ly
Reje
ctio
n
Rat
io
Input Frequency (Hz)
C045
-----
± 2.5*V
REF
----- ± 1.25*V
REF
----- ± 0.625*V
REF
------ +2.5*V
REF
------+1.25*V
REF
SBAS582C – JULY 2014 – REVISED APRIL 2015
10 Power-Supply Recommendations
The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD, while DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value
within the permissible range.
The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each
supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling
capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of
using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR)
performance of the device.
shows the PSRR of the device without using a decoupling capacitor. The
PSRR improves when the decoupling capacitors are used, as shown in
Code output near 32,769
Code output near 32,768
Figure 99. PSRR Without a Decoupling Capacitor
Figure 100. PSRR With a Decoupling Capacitor
11 Layout
11.1 Layout Guidelines
illustrates a PCB layout example for the ADS8684 and ADS8688.
•
Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the lower
side of the board while the digital connections are routed on the top side of the board.
•
Using a single dedicated ground plane is strongly encouraged.
•
Power sources to the ADS8684 and ADS8688 must be clean and well-bypassed. TI recommends using a
1-
μ
F, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating in close proximity to the analog
(AVDD) supply pins. For decoupling the digital (DVDD) supply pin, a 10-
μ
F, X7R-grade, 0805-size ceramic
capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the
bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, low
impedance paths.
•
There are two decoupling capacitors used for REFCAP pin. The first is a small, 1-
μ
F, X7R-grade, 0603-size
ceramic capacitor placed close to the device pins for decoupling the high-frequency signals and the second is
a 22-µF, X7R-grade, 1210-size ceramic capacitor to provide the charge required by the reference circuit of
the device. Both these capacitors must be directly connected to the device pins without any vias between the
pins and capacitors.
•
The REFIO pin also must be decoupled with a 10-µF ceramic capacitor, if the internal reference of the device
is used. The capacitor must be placed close to the device pins.
•
For the auxiliary channel, the fly-wheel RC filter components must be placed close to the device. Among
ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision.
The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties
over voltage, frequency, and temperature changes.
Copyright © 2014–2015, Texas Instruments Incorporated
57
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