0
5
10
15
20
25
30
-4
-3
-2
-1
0
1
Num
b
e
r
o
f
Device
s
Error in REFIO Voltage (mV)
C065
0
100
200
300
400
500
600
-1
-0.6
-0.2
0.2
0.6
1
Num
b
e
r
o
f
Device
s
Error in REFIO Voltage (mV)
C064
SBAS582C – JULY 2014 – REVISED APRIL 2015
The device internal reference is factory trimmed to a maximum initial accuracy of ±1 mV. The histogram in
shows the distribution of the internal voltage reference output taken from more than 3300 production
devices.
Figure 58. Internal Reference Accuracy at Room Temperature Histogram
The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical or thermal stress. Heating the device while being soldered to a PCB and any subsequent solder
re
fl
ow is a primary cause for shifts in the V
REF
value. The main cause of thermal hysteresis is a change in die
stress and therefore is a function of the package, die-attach material, and molding compound, as well as the
layout of the device itself.
In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer's
suggested reflow profile, as explained in the Application Report
AN-2029 Handling & Process Recommendations
. The internal voltage reference output is measured before and after the reflow process and the
typical shift in value is displayed in
. Although all tested units exhibit a positive shift in their output
voltages, negative shifts are also possible. Note that the histogram in
displays the typical shift for
exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount
components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple
reflows, solder the ADS8684 and ADS8688 in the second pass to minimize device exposure to thermal stress.
Figure 59. Solder Heat Shift Distribution Histogram
Copyright © 2014–2015, Texas Instruments Incorporated
27
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