Texas Instruments ADS868 Series Manual Download Page 38 | Manualshive

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1

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14

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16

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30

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32

SCLK

CS

B3

SDO

Data from sample N

B15

B14

B2

B1

B0

STDBY COMMAND

±

8200h

SDI

X

X

X

X

X

X

X

X

Sample N

Enters STDBY on

CS Rising Edge

CS can go high immediately after Standby

command or after reading frame data

1

2

14

15

16

Stays in STDBY
if SDI is LOW in

a data frame

ADS8684, ADS8688

SBAS582C – JULY 2014 – REVISED APRIL 2015

8.4.2.2 Frame Abort Condition (FRAME_ABORT)

As explained in the

Data Acquisition Example

section, the device digital interface is designed such that each data

frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit
command word on the SDI line. The device waits to execute the command until the last bit of the command is
received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If
the CS signal goes high for any reason before the data transmission is complete, the device goes into an
INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT
condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid
data on the SDO line.

8.4.2.3 STANDBY Mode (STDBY)

The devices support a low-power standby mode (STDBY) in which only part of the circuit is powered down. The
internal reference and buffer is not powered down, and therefore, the devices can be quickly powered up in 20
µs on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not
reset to the default values.

To enter STDBY mode, execute a valid write operation to the command register with a STDBY command of
8200h, as shown in

. The command is executed and the device enters STDBY mode on the next CS

rising edge following this write operation. The device remains in STDBY mode if no valid conversion command
(AUTO_RST or MAN_Ch_n) is executed and SDI remains low (refer to the

Continued Operation in the Selected

section) during the subsequent data frames. When the device operates in STDBY mode, the program

register settings can be updated (as explained in the

Program Register Read/Write Operation

section) using 16

SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the
SDO line because there is no ongoing conversion in STDBY mode. The program register read operation can
take place normally during this mode.

Figure 77. Enter and Remain in STDBY Mode Timing Diagram

38

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Summary of Contents for ADS868 Series

Page 1: ...t a throughput of 500 kSPS The devices feature integrated analog Input Overvoltage Protection Up to 20 V front end circuitry for each input channel with On Chip 4 096 V Reference with Low Drift overvoltage protection up to 20 V a 4 or 8 channel Excellent Performance multiplexer with automatic and manual scanning modes and an on chip 4 096 V reference with low 500 kSPS Aggregate Throughput temperat...

Page 2: ...leted footnote from Device Comparison table 4 Updated ESD Ratings table to current standards 6 Corrected package name in Thermal Information table 6 Changed Auxiliary Channel SINAD and SFDR typical specifications in Electrical Characteristics table 9 Changed tDZ_CSDO symbol in Timing Requirements table and Figure 1 11 Deleted clamp from second sentence of Overview section 21 Changed voltage range ...

Page 3: ...Y 2014 REVISED APRIL 2015 Changes from Original July 2014 to Revision A Page Made changes to product preview data sheet 1 Copyright 2014 2015 Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links ADS8684 ADS8688 ...

Page 4: ...rial communication Active low logic input 2 RST PD Digital input Dual functionality to reset or power down the device 3 DAISY Digital input Chain the data input during serial communication in daisy chain mode Active low logic input to enable the internal reference When low the internal reference is enabled 4 REFSEL Digital input REFIO becomes an output that includes the VREF voltage When high the ...

Page 5: ...og input channel 3 positive input Decouple with AIN_3GND on pin 23 23 AIN_3P Analog input Analog input channel 3 negative input Decouple with AIN_3P on pin 22 Analog input channel 4 positive input Decouple with AIN_4GND on pin 25 24 NC AIN_4GND Analog input No connection for the ADS8684 this pin can be left floating or connected to AGND Analog input channel 4 negative input Decouple with AIN_4P on...

Page 6: ...nput pins 6000 AIN_nP AIN_nGND Human body model HBM per ANSI ESDA JEDEC JS 001 1 Electrostatic V ESD V discharge All other pins 2000 Charged device model CDM per JEDEC specification JESD22 C101 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD ...

Page 7: ...ative input At TA 25 C zi Input impedance 0 85 1 1 15 MΩ B All input ranges Input impedance drift All input ranges 7 25 ppm C B VIN 2 25 With voltage at AIN_nP pin VIN µA A input range 2 5 VREF RIN VIN 2 00 With voltage at AIN_nP pin VIN µA A input range 1 25 VREF RIN VIN 1 60 With voltage at AIN_nP pin VIN IIkg in Input leakage current µA A input range 0 625 VREF RIN VIN 2 50 With voltage at AIN_...

Page 8: ... mV A input range 2 5 VREF At TA 25 C 0 5 1 mV A input range 1 25 VREF At TA 25 C EO Offset error 0 5 1 5 mV A input range 0 625 VREF At TA 25 C 0 5 2 mV A input range 0 to 2 5 VREF At TA 25 C 0 5 2 mV A input range 0 to 1 25 VREF At TA 25 C 0 5 0 75 mV A input range 2 5 VREF At TA 25 C 0 5 1 mV A input range 1 25 VREF Offset error matching At TA 25 C 0 5 1 5 mV A channel to channel input range 0 ...

Page 9: ...W 0 1 dB Small signal bandwidth 0 1 dB At TA 25 C all input ranges 2 5 kHz B AUXILIARY CHANNEL Resolution 16 Bits A V AUX_IN AUX_IN voltage range AUX_IN AUX_GND 0 VREF V A AUX_IN 0 VREF V A Operating input range AUX_GND 0 V A During sampling 75 pF C Ci Input capacitance During conversion 5 pF C IIkg in Input leakage current 100 nA A DNL Differential nonlinearity 0 99 0 6 1 5 LSB A INL Integral non...

Page 10: ...for specified 2 7 3 3 5 25 V B performance For the ADS8688 AVDD 5 V fS 13 16 mA A maximum and internal reference Dynamic IAVDD_DYN AVDD For the ADS8684 AVDD 5 V fS 8 5 11 5 mA A maximum and internal reference For the ADS8688 AVDD 5 V device not converting and internal 10 12 mA A reference IAVDD_STC Analog supply current Static For the ADS8684 AVDD 5 V device not converting and internal 5 5 8 5 mA ...

Page 11: ...CLK max 2 µs fSCLK Serial clock frequency fS max 17 MHz tSCLK Serial clock time period fS max 59 ns tCONV Conversion time 850 ns tDZ_CSDO Delay time CS falling to data enable 10 ns tD_CKCS Delay time last SCLK falling to CS rising 10 ns tDZ_CSDO Delay time CS rising to SDO going to 3 state 10 ns TIMING REQUIREMENTS tACQ Acquisition time 1150 ns tPH_CK Clock high time 0 4 0 6 tSCLK tPL_CK Clock low...

Page 12: ...Input Voltage V C001 2 5 VREF 1 25 VREF 0 625 VREF 2 5 VREF 1 25 VREF ADS8684 ADS8688 SBAS582C JULY 2014 REVISED APRIL 2015 www ti com 7 7 Typical Characteristics At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Input range 2 5 VREF Figure 2 Input I V Characteristic Figure 3 Input Current vs Temperature Number of samples 1160 Figure 4 Input I...

Page 13: ...4 ADS8688 www ti com SBAS582C JULY 2014 REVISED APRIL 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Mean 32767 9 sigma 0 76 input 0 V Mean 32767 75 sigma 0 65 input 1 25 VREF range 0 625 VREF range 2 5 VREF Figure 8 DC Histogram for Mid Scale Inputs 0 625 VREF Figure 9 DC Histogram for Mid Scale Input...

Page 14: ... 1 5 2 0 16384 32768 49152 65536 Integral Nonlinearity LSB Codes LSB C016 ADS8684 ADS8688 SBAS582C JULY 2014 REVISED APRIL 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 1 25 VREF Range 0 625 VREF Figure 14 Typical INL for All Codes Figure 15 Typical INL for All Codes Range 2 5 VREF Ra...

Page 15: ...nimum 2 1 0 1 2 40 7 26 59 92 125 Integral Nonlinearity LSB Free Air Temperature oC C021 Maximum Minimum ADS8684 ADS8688 www ti com SBAS582C JULY 2014 REVISED APRIL 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Range 0 625 VREF Figure 21 INL vs Temperature 2 5 VREF Figure 20 INL vs Temp...

Page 16: ... Gain Drift ppm ºC C027 ADS8684 ADS8688 SBAS582C JULY 2014 REVISED APRIL 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Range 2 5 VREF Figure 26 Gain Error vs Temperature Across Input Ranges Figure 27 Typical Histogram for Gain Error Drift Range 2 5 VREF Figure 28 Gain Error vs Temperature A...

Page 17: ...0000 100000 150000 200000 250000 Amplitude dB Input Frequency Hz C033 ADS8684 ADS8688 www ti com SBAS582C JULY 2014 REVISED APRIL 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Number of points 64k fIN 1 kHz SNR 89 6 dB Number of points 64k fIN 1 kHz SNR 90 93 dB SINAD 89 5 dB THD 106 dB SFDR 107 dB SI...

Page 18: ...tion Ratio dB Free AirTemperature oC C038 2 5 VREF 1 25 VREF 0 625 VREF 2 5 VREF 1 25 VREF 120 110 100 90 80 10 2010 4010 6010 8010 Total Harmonic Distortion dB Input Frequency Hz C039 2 5 VREF 1 25 VREF 0 625 VREF 2 5 VREF 1 25 VREF ADS8684 ADS8688 SBAS582C JULY 2014 REVISED APRIL 2015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fS...

Page 19: ...r Temperature oC C057 ADS8684 ADS8688 www ti com SBAS582C JULY 2014 REVISED APRIL 2015 Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Input 2 maximum input voltage Figure 44 Isolation Crosstalk vs Frequency for Figure 45 AVDD Current vs Temperature for the ADS8688 Overrange Inputs fS 500 kSPS Figure 47 AVDD...

Page 20: ...015 www ti com Typical Characteristics continued At TA 25 C AVDD 5 V DVDD 3 V internal reference VREF 4 096 V and fSAMPLE 500 kSPS unless otherwise noted Figure 50 AVDD Current vs Temperature Power Down 20 Submit Documentation Feedback Copyright 2014 2015 Texas Instruments Incorporated Product Folder Links ADS8684 ADS8688 ...

Page 21: ... programmable gain amplifier PGA and a second order antialiasing filter that conditions the input signal before being fed into a 4 or 8 channel analog multiplexer MUX The output of the MUX is digitized using a 16 bit analog to digital converter ADC based on the successive approximation register SAR architecture This overall system can achieve a maximum throughput of 500 kSPS combined across all ch...

Page 22: ... 1 25 VREF range can be assigned to AIN_2P the 0 V to 2 5 VREF range can be assigned to AIN_3P and so forth The devices sample the voltage difference AIN_nP AIN_nGND between the selected analog input channel and the AIN_nGND pin The devices allow a 0 1 V range on the AIN_nGND pin for all analog input channels This feature is useful in modular systems where the sensor or signal conditioning block i...

Page 23: ...supply voltage AVDD 5 V or offers a low impedance of 30 kΩ the internal overvoltage protection circuit can withstand up to 20 V on the analog input pins Table 1 Input Overvoltage Protection Limits When AVDD 5 V or Offers a Low Impedance of 30 kΩ 1 INPUT CONDITION TEST ADC COMMENTS VOVP 20 V CONDITION OUTPUT All input VIN VRANGE Within operating range Valid Device functions as per data sheet specif...

Page 24: ...e 2 Input Overvoltage Protection Limits When AVDD Floating with Impedance 30 kΩ 1 INPUT CONDITION TEST ADC OUTPUT COMMENTS VOVP 11 V CONDITION Device is not functional but is protected internally by VIN VOVP Within overvoltage range All input ranges Invalid the OVP circuit This usage condition may cause irreversible damage VIN VOVP Beyond overvoltage range All input ranges Invalid to the device 1 ...

Page 25: ...IT 3 BIT 2 BIT 1 BIT 0 2 5 VREF 0 0 0 0 1 25 VREF 0 0 0 1 0 625 VREF 0 0 1 0 0 to 2 5 VREF 0 1 0 1 0 to 1 25 VREF 0 1 1 0 8 3 5 Second Order Low Pass Filter LPF In order to mitigate the noise of the front end amplifiers and gain resistors of the PGA each analog input channel of the ADS8684 and ADS8688 features a second order antialiasing LPF at the output of the PGA The magnitude and phase respons...

Page 26: ...selected as in the ADS8684 and so forth Refer to Table 6 for command register settings to switch between the auto scan mode and manual mode for individual analog channels 8 3 8 Reference The ADS8684 and ADS8688 can operate with either an internal voltage reference or an external voltage reference using the internal buffer The internal or external reference selection is determined by an external RE...

Page 27: ...material and molding compound as well as the layout of the device itself In order to illustrate this effect 80 devices were soldered using lead free solder paste with the manufacturer s suggested reflow profile as explained in the Application Report AN 2029 Handling Process Recommendations SNOA550 The internal voltage reference output is measured before and after the reflow process and the typical...

Page 28: ...1 Internal Reference Temperature Drift Histogram REFIO Across Supply and Temperature 8 3 8 2 External Reference For applications that require a better reference voltage or a common reference voltage for multiple devices the ADS8684 and ADS8688 offer a provision to use an external reference along with an internal buffer to drive the ADC reference pin In order to select the external reference mode e...

Page 29: ...y Channel The devices include a single ended auxiliary input channel AUX_IN and AUX_GND The AUX channel provides direct interface to an internal high precision 16 bit ADC through the multiplexer because this channel does not include the front end analog signal conditioning that the other analog input channels have The AUX channel supports a single unipolar input range of 0 V to VREF because there ...

Page 30: ...plifier with low output impedance is required to meet the ac performance of the internal 16 bit ADC Some key specifications of the input driving amplifier are discussed below Small signal bandwidth The small signal bandwidth of the input driving amplifier must be much higher than the bandwidth of the AUX input to ensure that there is no attenuation of the input signal resulting from the bandwidth ...

Page 31: ...annel devices that support single ended bipolar and unipolar input ranges on all input channels The output of the devices is in straight binary format for both bipolar and unipolar input ranges The format for the output codes is the same across all analog channels The ideal transfer characteristic for each ADC channel for all input ranges is shown in Figure 69 The full scale range FSR for each inp...

Page 32: ...r the data interface All synchronous accesses to the device are timed with respect to the falling edges of the SCLK signal 8 4 1 1 3 SDI Input SDI is the serial data input line SDI is used by the host processor to program the internal device registers for device configuration At the beginning of each data frame the CS signal goes low and the data on the SDI line are read by the device at every fal...

Page 33: ... enters PWR_DN mode and the program registers are reset to default tPL_RST_PD 400 ns value The devices can be placed into power down PWR_DN mode by pulling the RST PD pin to a logic low state for at least 400 ns The RST PD pin is asynchronous to the clock thus RST PD can be triggered at any time regardless of the status of other pins including the analog input channels When the device is in power ...

Page 34: ...ts on SDO until the 16th falling edge appears on the SCLK input Because the ADC conversion time is fixed the maximum value is given in the Electrical Characteristics table the 16th SCLK falling edge must appear after the internal conversion is over otherwise data output from the device is incorrect Therefore the SCLK frequency cannot exceed a maximum value as provided in the Timing Requirements Se...

Page 35: ...iagram At the falling edge of the CS signal all devices sample the input signal at their respective selected channels and enter into conversion phase For the first 16 SCLK cycles the internal register settings for the next conversion can be entered using the SDI line which is common to all devices in the chain During this time period the SDO outputs for all devices remain low At the end of convers...

Page 36: ... controlled by separate CS control lines from the host controller Figure 75 Star Topology Connection Schematic The timing diagram for a typical data frame in the star topology is the same as in a stand alone device operation as illustrated in Figure 72 The data frame for a particular device starts with the falling edge of the CS signal and ends when the CS signal goes high Because the host control...

Page 37: ...he different modes of the device After power up the program registers wake up with the default values and require appropriate configuration settings before performing any conversion The diagram in Figure 76 explains how to switch the device from one mode of operation to another Figure 76 State Transition Diagram 8 4 2 1 Continued Operation in the Selected Mode NO_OP Holding the SDI line low contin...

Page 38: ...BY Mode STDBY The devices support a low power standby mode STDBY in which only part of the circuit is powered down The internal reference and buffer is not powered down and therefore the devices can be quickly powered up in 20 µs on exiting the STDBY mode When the device comes out of STDBY mode the program registers are not reset to the default values To enter STDBY mode execute a valid write oper...

Page 39: ...the next CS falling edge the device samples the analog input at the channel selected by the MAN_CH_n command or the first channel of the AUTO_RST mode sequence To ensure that the input signal is sampled correctly keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device internal circuitry can be fully powered up and biased properly before taking the sample The data ou...

Page 40: ...software power down To enter PWR_DN mode using software execute a valid write operation on the command register with a software PWR_DN command of 8300h as shown in Figure 79 The command is executed and the device enters PWR_DN mode on the next CS rising edge following this write operation The device remains in PWR_DN mode if no valid conversion command AUTO_RST or MAN_Ch_n is executed and SDI rema...

Page 41: ...lete frame of 32 SCLK cycles The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control register 01h to 02h in the program register refer to the Program Register Map section In this mode the devices continuously cycle through the selected channels in ascending order beginning with the lowest channel and converting all channels selected in the program regi...

Page 42: ... be pulled high immediately after the MAN_Ch_n command or after reading the output data of the frame However in order to accurately acquire and convert the input signal on the next channel the command frame must be a complete frame of 32 SCLK cycles Refer to Table 6 for a list of commands to select individual channels during MAN_Ch_n mode Figure 83 Enter MAN_Ch_n Scan Mode Timing Diagram The manua...

Page 43: ...during an automatic scan using the AUTO_RST command When the reset command is received the ongoing auto mode sequence is reset and restarts from the lowest selected channel in the sequence In MAN_Ch_n mode the same input channel is selected during every data conversion frame The input command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6 If a particular input ch...

Page 44: ...8500h as shown in Figure 87 The device remains in RST mode if no valid conversion command AUTO_RST or MAN_Ch_n is executed and SDI remains low refer to the Continued Operation in the Selected Mode NO_OP section during the subsequent data frames When the device operates in RST mode the program register settings can be updated as explained in the Program Register Read Write Operation section using 1...

Page 45: ...wn 1 0 0 0 0 0 1 1 0000 0000 8300h Device is powered down PWR_DN Reset program registers 1 0 0 0 0 1 0 1 0000 0000 8500h Program register is reset to default RST Auto Ch Sequence with Reset 1 0 1 0 0 0 0 0 0000 0000 A000h Auto mode enabled following a reset AUTO_RST Manual Ch 0 Selection 1 1 0 0 0 0 0 0 0000 0000 C000h Channel 0 input is selected MAN_Ch_0 Manual Ch 1 Selection 1 1 0 0 0 1 0 0 0000...

Page 46: ...t SCLK cycles the device outputs this 8 bit data that is written into the register This data readback allows verification to determine if the correct data are entered into the device A typical timing diagram for a program register write cycle is shown in Figure 88 Table 7 Write Cycle Command Word REGISTER ADDRESS WR RD DATA PIN Bits 15 9 Bit 8 Bits 7 0 SDI ADDR 6 0 1 DIN 7 0 Figure 88 Program Regi...

Page 47: ...07h 00h 0 0 0 0 Range Select Channel 2 3 0 Channel 3 Input Range 08h 00h 0 0 0 0 Range Select Channel 3 3 0 Channel 4 Input Range 09h 00h 0 0 0 0 Range Select Channel 4 3 0 Channel 5 Input Range 0Ah 00h 0 0 0 0 Range Select Channel 5 3 0 Channel 6 Input Range 0Bh 00h 0 0 0 0 Range Select Channel 6 3 0 Channel 7 Input Range 0Ch 00h 0 0 0 0 Range Select Channel 7 3 0 COMMAND READ BACK Read Only Comm...

Page 48: ... behavior A read operation on any of these bits or registers outputs all 1 s on the SDO line Table 10 AUTO_SEQ_EN Field Descriptions Bit Field Type Reset Description Channel 7 enable 7 CH7_EN R W 1h 0 Channel 7 is not selected for sequencing in AUTO_RST mode 1 Channel 7 is selected for sequencing in AUTO_RST mode Channel 6 enable 6 CH6_EN R W 1h 0 Channel 6 is not selected for sequencing in AUTO_R...

Page 49: ...6 CH6_PD R W 0h included in the AUTO_RST sequence 1 The analog front end on channel 6 is powered down and channel 6 cannot be included in the AUTO_RST sequence Channel 5 power down 0 The analog front end on channel 5 is powered up and channel 5 can be 5 CH5_PD R W 0h included in the AUTO_RST sequence 1 The analog front end on channel 5 is powered down and channel 5 cannot be included in the AUTO_R...

Page 50: ... Conversion result for selected 000 SDO pulled low no latency channel MSB first 16th SCLK falling edge Conversion result for selected Channel 001 SDO pulled low no latency channel MSB first address 1 16th SCLK falling edge Conversion result for selected Channel Device SDO pulled 010 no latency channel MSB first address 1 address 1 low 16th SCLK falling edge Conversion result for selected Channel D...

Page 51: ... for the ADS8688 0000 Input range is set to 2 5 x VREF 3 0 Range_CHn 3 0 R W 0h 0001 Input range is set to 1 25 x VREF 0010 Input range is set to 0 625 x VREF 0101 Input range is set to 0 to 2 5 x VREF 0110 Input range is set to 0 to 1 25 x VREF 8 5 2 3 4 Command Read Back Register address 3Fh This register allows the device mode of operation to be read On execution of this command the device outp...

Page 52: ...evices include an integrated analog front end for each input channel and an integrated precision reference with a buffer As such this device family does not require any additional external circuits for driving the reference or analog input pins of the ADC 9 2 Typical Applications 9 2 1 Phase Compensated 8 Channel Multiplexed Data Acquisition System for Power Automation Figure 95 8 Channel Multiple...

Page 53: ...ost applications using passive RC filters or multi stage filters in front of the ADC is preferred to reduce the noise of the input signal The software algorithm implemented in this design uses the discrete fourier transform DFT method to calculate and track the input signal frequency get the exact phase angle of the individual signal calculate the phase difference and implement phase compensation ...

Page 54: ... Hz Measured Phase Difference Theoretical Phase Difference C066 ADS8684 ADS8688 SBAS582C JULY 2014 REVISED APRIL 2015 www ti com Figure 96 Measured and Theoretical Phase Difference Between Consecutive Channels For a step by step design procedure circuit schematics bill of materials PCB files simulation results and test results refer to Phase Compensated 8 Channel Multiplexed Data Acquisition Syste...

Page 55: ...nel single supply SAR ADC with an on chip PGA and reference The on chip PGA provides a high input impedance typically 1 MΩ and filters noise interference The on chip 4 096 V ultra low drift voltage reference is used as the reference for the ADC core The digital isolation is achieved using an ISO7141CC and ISO1541D The host microcontroller communicates with a TCA6408A an 8 bit I2 C I O expander ove...

Page 56: ...dB 0 V to 5 V 87 5 dB min 88 48 dB 10 V 14 66 14 80 2 ENOB Bits 0 V 10 V 14 41 14 58 0 V to 5 V 14 24 14 41 10 V 2 1 77 3 Maximum INL LSB 0 V 10 V 2 1 64 0 V to 5 V 2 1 35 10 V 2 1 47 4 Minimum INL LSB 0 V 10 V 2 1 36 0 V to 5 V 2 1 37 The accuracy performance for this design for the 10 24 V input range is shown in Figure 98 Figure 98 System Accuracy Performance in 2 5 VREF Input Range For a step ...

Page 57: ...eference input signals away from the digital noise In this layout example the analog input and reference signals are routed on the lower side of the board while the digital connections are routed on the top side of the board Using a single dedicated ground plane is strongly encouraged Power sources to the ADS8684 and ADS8688 must be clean and well bypassed TI recommends using a 1 μF X7R grade 0603...

Page 58: ...4 AIN_4GND 23 AIN_3P 22 AIN_3GND 21 AIN_2P 20 AIN_2GND 1µF 22µF GND GND GND GND GND 10µF GND 1µF GND CS SCLK SDO SDI RST PD REFSEL DAISY Optional RC Filter for Channel AIN_0 to AIN_7 1µF Digital Pins Analog Pins 10µF When using internal VREF ADS8684 ADS8688 SBAS582C JULY 2014 REVISED APRIL 2015 www ti com 11 2 Layout Example Figure 101 Board Layout for the ADS8684 and ADS8688 58 Submit Documentati...

Page 59: ...Click here 12 3 Trademarks SPI is a trademark of Motorola All other trademarks are the property of their respective owners 12 4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can r...

Page 60: ...le for use in specified lead free processes TI may reference these types of products as Pb Free RoHS Exempt TI defines RoHS Exempt to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption Green TI defines Green to mean the content of Chlorine Cl and Bromine Br based flame retardants meet JS709B low halogen requirements of 1000ppm threshold Antimony...

Page 61: ...ing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis ...

Page 62: ...s SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant ADS8684IDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 ADS8688IDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 20 Mar 2015 Pack Materials Page 1 ...

Page 63: ...Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS8684IDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 ADS8688IDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 PACKAGE MATERIALS INFORMATION www ti com 20 Mar 2015 Pack Materials Page 2 ...

Page 64: ...ers Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change without notice 3 This dimension does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15 mm per side 4 This dimension does not include interlead flash Interlead flash shall not exceed 0 25 mm per side 5 Ref...

Page 65: ...PC 7351 may have alternate designs 7 Solder mask tolerances between and around signal pads can vary based on board fabrication site LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE 10X SYMM SYMM 1 19 20 38 15 000 METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK DETAILS NON SOLDER MASK DEFINED PREFERRED SOLDER MASK DEFINED 4220221 A 05 2020...

Page 66: ...continued 8 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations 9 Board assembly site may have different recommendations for stencil design SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL SCALE 10X SYMM SYMM 1 19 20 38 4220221 A 05 2020 ...

Page 67: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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