1
2
12
13
14
15
16
SCLK
CS
SDO
AUTO_RST Command
MAN_CH_n Command
SDI
9
10
11
3
4
5
6
7
8
Device exits PWR_DN Mode, but
waits 15ms for 16-bit settling
First 16-bit accurate data
frame after recovery from
PWR_DN mode
Invalid
Data
1
2
14
15
16
17
18
30
31
32
SCLK
CS
B3
SDO
Data from sample N
B15
B14
B2
B1
B0
PWR_DN COMMAND
±
8300h
SDI
X
X
X
X
X
X
X
X
Sample N
Enters PWR_DN on
CS Rising Edge
CS can go high immediately after PWR_DN
command or after reading frame data
1
2
14
15
16
Stays in PWR_DN
if SDI is LOW in a
data frame
SBAS582C – JULY 2014 – REVISED APRIL 2015
8.4.2.4 Power-Down Mode (PWR_DN)
The devices support a hardware and software power-down mode (PWR_DN) in which all internal circuitry is
powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to
power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating
in the internal reference mode (REFSEL = 0). The hardware power mode for the device is explained in the
section. The primary difference between the hardware and software power-down modes is that
the program registers are reset to default values when the devices wake up from hardware power-down, but the
previous settings of the program registers are retained when the devices wake up from software power-down.
To enter PWR_DN mode using software, execute a valid write operation on the command register with a
software PWR_DN command of 8300h, as shown in
. The command is executed and the device enters
PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode
if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (refer to the
Continued Operation in the Selected Mode
section) during the subsequent data frames. When the device
operates in PWR_DN mode, the program register settings can be updated (as explained in the
section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then
the device returns invalid data on the SDO line because there is no ongoing conversion in PWR_DN mode. The
program register read operation can take place normally during this mode.
Figure 79. Enter and Remain in PWR_DN Mode Timing Diagram
In order to exit from PWR_DN mode a valid 16-bit write command must be executed, as shown in
. The
device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode
(REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle
to the required accuracy before valid conversion data are output for the selected input channel.
Figure 80. Exit PWR_DN Mode Timing Diagram
40
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