1
2
15
16
SCLK
CS
SDO
ADDR [6:0]
RD
X X X X X X
SDI
9
10
6
7
8
DOUT [7:0]
23
24
17
18
1
2
15
16
SCLK
CS
SDO
ADDR [6:0]
WR
DIN [7:0]
SDI
9
10
6
7
8
Data written into register, DIN [7:0]
23
24
17
18
X X X X
Sample
N
SBAS582C – JULY 2014 – REVISED APRIL 2015
8.5.2.1 Program Register Read/Write Operation
The program register is a 16-bit read or write register. There must be a minimum of 24 SCLKs after the CS
falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low
as well. The device receives the command (as shown in
and
) through SDI where the first seven
bits (bits 15-9) represent the register address and the eighth bit (bit 8) is the write or read instruction.
For a write cycle, the next eight bits (bits 7-0) on SDI are the desired data for the addressed register. Over the
next eight SCLK cycles, the device outputs this 8-bit data that is written into the register. This data readback
allows verification to determine if the correct data are entered into the device. A typical timing diagram for a
program register write cycle is shown in
Table 7. Write Cycle Command Word
REGISTER ADDRESS
WR/RD
DATA
PIN
(Bits 15-9)
(Bit 8)
(Bits 7-0)
SDI
ADDR[6:0]
1
DIN[7:0]
Figure 88. Program Register Write Cycle Timing Diagram
For a read cycle, the next eight bits (bits 7-0) on SDI are
don’t care
bits and SDO stays low. From the 16th SCLK
falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in
MSB-first fashion. A typical timing diagram for a program register read cycle is shown in
Table 8. Read Cycle Command Word
REGISTER ADDRESS
WR/RD
DATA
PIN
(Bits 15-9)
(Bit 8)
(Bits 7-0)
SDI
ADDR[6:0]
0
XXXXX
SDO
0000 000
0
DOUT[7:0]
Figure 89. Program Register Read Cycle Timing Diagram
46
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