T-Core
User Manual
22
January 14, 2020
There are two Transient Voltage Suppressor diode arrays used to implement ESD protection for 8
GPIO user pins.
shows the connection between the TMD header and MAX 10 FPGA.
the pin assignment of 2x6 TMD header.
Figure 2-24 Connections between the 2x6 TMD header and MAX 10 FPGA
Table 2-9 Pin Assignment of 2x6 TMD Header.
Signal Name
FPGA Pin No.
Description
I/O Standard
TMD_D[0]
PIN_AB8
GPIO Connection [0]
3.3-V LVTTL
TMD_D[1]
PIN_AA8
GPIO Connection [1]
3.3-V LVTTL
TMD_D[2]
PIN_AA5
GPIO Connection [2]
3.3-V LVTTL
TMD_D[3]
PIN_AB5
GPIO Connection [3]
3.3-V LVTTL
TMD_D[4]
PIN_AB7
GPIO Connection [4]
3.3-V LVTTL
TMD_D[5]
PIN_AA7
GPIO Connection [5]
3.3-V LVTTL
TMD_D[6]
PIN_AB6
GPIO Connection [6]
3.3-V LVTTL
TMD_D[7]
PIN_AA6
GPIO Connection [7]
3.3-V LVTTL
2
2
.
.
6
6
1
1
x
x
1
1
0
0
A
A
/
/
D
D
C
C
o
o
n
n
v
v
e
e
r
r
t
t
e
e
r
r
a
a
n
n
d
d
A
A
n
n
a
a
l
l
o
o
g
g
I
I
n
n
p
p
u
u
t
t
The board has eight analog inputs are connected to MAX 10 FPGA ADC1, through a 1x10 header
(JP1) input. Any analog inputs signals sourced through the header JP1 are RC filtered by the Analog
Front-End circuit, and the maximum allowable input voltage 2.5V per the MAX 10 FPGA ADC IP
block.
