T-Core
User Manual
17
January 14, 2020
(closest to the edge of the board), it provides a low logic level to the FPGA, and when the switch is
in another position, it provides a high logic level.
list the pin assignments of the user
switches.
Figure 2-16 Connections between the slide switches and MAX 10 FPGA
Table 2-5 Pin Assignment of Slide Switches
Signal Name
FPGA Pin No.
Description
I/O Standard
SW[0]
PIN_AB16
Dip Switch[0]
3.3-V LVTTL
SW[1]
PIN_Y16
Dip Switch[1]
3.3-V LVTTL
SW[2]
PIN_V16
Dip Switch[2]
3.3-V LVTTL
SW[3]
PIN_AB17
Dip Switch[3]
3.3-V LVTTL
◼
User-Defined LEDs
There are also four user-controllable LEDs connected to FPGA on the board. Each LED is driven
directly and individually by a pin on the MAX 10 FPGA; driving its associated pin to a high logic
level turns the LED on, and driving the pin low turns it off.
list the pin assignment of user LEDs.
