TR5-F40W
User
Manual
69
June 20, 2018
Figure 5-7
Menu of Demo Program
In the temperature test, the program will display local temperature and remote temperature. The
remote temperature is the FPGA temperature, and the local temperature the board temperature
where the temperature sensor located.
In the external PLL programming test, the program will program the PLL first, and subsequently
will use TERASIC QSYS custom CLOCK_COUNTER IP to count the clock count in a specified
period to check whether the output frequency is changed as configured. To avoid a Quartus II
compilation error, dummy transceiver controllers are created to receive the clock from the external
PLL. Users can ignore the functionality of the transceiver controller in the demonstration.
The example uses the CDCM6100x_Config IP which is generated by system builder to
programming CDCM61004. The Nios II uses PIO controllers to control the IP. First, Nios II
specifies the desired output frequency through IP's
desired_freq
pin, then active the PPL
recalibration by toggle IP's
recal_n
pin. For Si570 programming, please note the device I2C address
is 0x00. Also, before configuring the output frequency, users must freeze the DCO (bit 4 of Register
137) first. After configuring the output frequency, users must un-freeze the DCO and assert the
NewFreq bit (bit 7 of Register 135).
Design Tools
Quartus II 12.0
Nios II Eclipse 12.0
Demonstration Source Code
Quartus II Project directory: Nios_BASIC_DEMO
Nios II Eclipse: Nios_BASIC_DEMO\Software
