Terasic ALTERA TR5-F40W, User Manual

Page: 27 / 73

TR5-F40W User
Manual
27 www.terasic.com
June 20, 2018
Figure 2-13 Connection between the SFP+ and Stratix V GX FPGA
Table 2-14 to Table 2-17 list the SFP+ A, B, C and D pin assignments and signal names relative to
the Stratix V GX device.
Table 2-14 SFP+ A Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard
Stratix V GX
Pin Number
SFPA_TX_p Transmitter data 1.4-V PCML PIN_AA4
SFPA_TX_n Transmitter data 1.4-V PCML PIN_AA3
SFPA_RX_p Receiver data 1.4-V PCML PIN_AB2
SFPA_RX_n Receiver data 1.4-V PCML PIN_AB1
SFPA_LOS Signal loss indicator 2.5V PIN_AE10
SFPA_MOD0_PRSNT_n Module present 2.5V PIN_AD9
SFPA_MOD1_SCL Serial 2-wire clock 2.5V PIN_AC9
SFPA_MOD2_SDA Serial 2-wire data 2.5V PIN_AC12
SFPA_RATESEL0 Rate select 0 2.5V PIN_AE11
SFPA_RATESEL1 Rate select 1 2.5V PIN_AE9
SFPA_TXDISABLE
Turns off and disables the transmitter
output
2.5V PIN_AB9
SFPA_TXFAULT Transmitter fault 2.5V PIN_AB12
Table 2-15 SFP+ B Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard
Stratix V GX
Pin Number
SFPB_TX_p Transmitter data 1.4-V PCML PIN_AE4
SFPB_TX_n Transmitter data 1.4-V PCML PIN_AE3