Terasic ALTERA TR5-F40W User Manual Download Page 36

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TR5-F40W

User

Manual

www.terasic.com

June 20, 2018

Figure 2-18 HSMC I/O Configuration Header

Table 2-21

HSMC IO Standard Indicators

I/O Standard

Jump

Position

Jump Position (J3)

LED Status (D25)

1.5V

J3.1

– J3.2

1.8V

J3.3

– J3.4

2.5V

J3.5

– J3.6

(1)

Users who connect a daughter card onto the HSMC ports need to pay close attention to the

I/O standard between HSMC connector pins and daughter card system. For example, if the

Summary of Contents for ALTERA TR5-F40W

Page 1: ...TR5 F40W User Manual 1 www terasic com June 20 2018...

Page 2: ...5 CLOCK CIRCUIT 18 2 6 RS422 SERIAL PORT 20 2 7 FLASH MEMORY 21 2 8 SSRAM 24 2 9 SPF PORTS 26 2 10 PCI EXPRESS 29 2 11 SATA 31 2 12 HSMC HIGH SPEED MEZZANINE CARD 34 CHAPTER 3 SYSTEM BUILDER 42 3 1 IN...

Page 3: ...TR5 F40W User Manual 3 www terasic com June 20 2018 5 3 SI570 AND CDCM PROGRAMMING NIOS II 68 ADDITIONAL INFORMATION 73...

Page 4: ...ivers that transfer at a maximum of 12 5 Gbps allowing the TR5 F40W to be fully compliant with version 3 0 of SATA version 3 0 of the PCI Express standard as well as allowing an ultra low latency stra...

Page 5: ...50MHz Oscillator o Programmable oscillators Si570 and CDCM61004 o SMA connector for external clock input output Memory o SSRAM o FLASH Communication Ports o Four SFP connectors o One SATA host port o...

Page 6: ...aximum flexibility for the users all key components are connected with the Stratix V GX FPGA device Thus users can configure the FPGA to implement any system design Figure 1 1 Block diagram of the TR5...

Page 7: ...2MB SSRAM 256MB FLASH General user I O 10 user controllable LEDs 4 user push buttons 4 user slide switches On Board Clock 50MHz oscillator Programmable oscillators providing clock for 10G SFP transcei...

Page 8: ...Two Serial ATA ports SATA 3 0 standard at 6Gbps signaling rate Four SFP ports Four SFP connector 10 Gbps PCI Express x8 edge connector Support for PCIe Gen1 2 3 Edge connector for PC motherboard with...

Page 9: ...d O Ov ve er rv vi ie ew w Figure 2 1 is the top and bottom view of the TR5 F40W development board It depicts the layout of the board and indicates the location of the connectors and key components U...

Page 10: ...f the FPGA using stored images from the flash memory on power up For programming via on board USB Blaster II the following procedures show how to download a configuration bit stream into the Stratix V...

Page 11: ...m Controller is actively configuring the FPGA Driven by the MAX II CPLD EPM2210 System Controller with the Embedded Blaster CPLD D17 Error Illuminates when the MAX II CPLD EPM2210 System Controller fa...

Page 12: ...Short Select VCCIO 1 5V output Open Setup PCI Express Control DIP switch The PCI Express Control DIP switch SW8 is provided to enable or disable different configurations of the PCIe Connector Table 2...

Page 13: ...ions as shown in Figure 2 4 Figure 2 4 6 Position DIP switch for Configure Mode Select Flash Image for Configuration The Image Select DIP switch SW5 is provided to specify the image for configuration...

Page 14: ...he USB Blaster SW6 3 selects the JTAG chain A more detailed explanation can be found in Chapter 2 12 JTAG Chain on HSMC Table 2 4 SW6 JTAG Chain DIP Switch Board Reference Signal Name Description Defa...

Page 15: ...gic level or a low logic level when it is not pressed or pressed respectively Table 2 5 lists the board references signal names and their corresponding Stratix V GX device pin numbers Table 2 5 Push b...

Page 16: ...Pin Assignments Schematic Signal Names and Functions Board Reference Schematic Signal Name Description I O Standard Stratix V GX Pin Number SW0 SW0 High logic level when SW in the UPPER position 2 5...

Page 17: ...quipped with a temperature sensor MAX1619 which provides temperature sensing and over temperature alert These functions are accomplished by connecting the temperature sensor to the internal temperatur...

Page 18: ...grammable oscillators Figure 2 9 shows the default frequencies of on board all external clocks going to the Stratix V GX FPGA The figures also show an off board external clock from PCI Express Host to...

Page 19: ...t SFP transceiver Figure 2 10 Control Circuits of Programmable Oscillators Table 2 9 lists the clock source signal names default frequency and their corresponding Stratix V GX device pin numbers Table...

Page 20: ...GX Pin Number Description Si570 U10 CLOCK_SCL 2 5 V PIN_AD15 I2C bus direct connected with Si570 CLOCK_SDA 2 5 V PIN_AD16 CDCM61004 U27 CLK_RST_n 2 5 V PIN_AC15 Device reset active low CLK_CE 2 5 V P...

Page 21: ...er Input The data is sent from FPGA PIN_H17 RS422_RE_n Receiver Enable A low enables the receiver A high input forces the receiver output into a high impedance state PIN_L16 RS422_TE Internal Terminat...

Page 22: ...hematic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix V GX Pin Number FSM_A0 Address bus 2 5 V PIN_AW22 FSM_A1 Address bus 2 5 V PIN_AV23 FSM_A2 Address bus 2 5 V P...

Page 23: ...26 FSM_D4 Data bus 2 5 V PIN_AG24 FSM_D5 Data bus 2 5 V PIN_AG23 FSM_D6 Data bus 2 5 V PIN_AC27 FSM_D7 Data bus 2 5 V PIN_AC26 FSM_D8 Data bus 2 5 V PIN_AA26 FSM_D9 Data bus 2 5 V PIN_AF23 FSM_D10 Dat...

Page 24: ...ich connects to flash memory SSRAM and the MAX II CPLD EEPM2210 System Controller Table 2 13 lists the SSRAM pin assignments signal names relative to the Stratix V GX device in respectively Table 2 13...

Page 25: ...M_D6 Data bus 2 5 V PIN_AC27 FSM_D7 Data bus 2 5 V PIN_AC26 FSM_D8 Data bus 2 5 V PIN_AA26 FSM_D9 Data bus 2 5 V PIN_AF23 FSM_D10 Data bus 2 5 V PIN_AG22 FSM_D11 Data bus 2 5 V PIN_AF22 FSM_D12 Data b...

Page 26: ...V PIN_AL26 SSRAM_WE_n Write enable 2 5 V PIN_AK29 SSRAM_GW_n Synchronous Burst Address Advance 2 5 V PIN_AL30 SSRAM_ADV_n Address Status Controller 2 5 V PIN_AN26 SSRAM_ADSC_n Address Status Controll...

Page 27: ...ata 1 4 V PCML PIN_AB2 SFPA_RX_n Receiver data 1 4 V PCML PIN_AB1 SFPA_LOS Signal loss indicator 2 5V PIN_AE10 SFPA_MOD0_PRSNT_n Module present 2 5V PIN_AD9 SFPA_MOD1_SCL Serial 2 wire clock 2 5V PIN_...

Page 28: ...n Receiver data 1 4 V PCML PIN_AP1 SFPC_LOS Signal loss indicator 2 5V PIN_AK12 SFPC_MOD0_PRSNT_n Module present 2 5V PIN_AH9 SFPC_MOD1_SCL Serial 2 wire clock 2 5V PIN_AH10 SFPC_MOD2_SDA Serial 2 wir...

Page 29: ...and PCI Express The PCI Express interface supports complete PCI Express Gen1 at 2 5Gbps lane Gen2 at 5 0Gbps lane and Gen3 at 8 0Gbps lane protocol stack solution compliant to PCI Express base specif...

Page 30: ...it bus 1 4 V PCML PIN_AL37 PCIE_TX_p4 Add in card transmit bus 1 4 V PCML PIN_AG36 PCIE_TX_n4 Add in card transmit bus 1 4 V PCML PIN_AG37 PCIE_TX_p5 Add in card transmit bus 1 4 V PCML PIN_AE36 PCIE_...

Page 31: ...Hot plug detect x4 PCIe slot enabled using SW8 dip switch PCIE_PRSNT2n_x8 Hot plug detect x8 PCIe slot enabled using SW8 dip switch 2 2 1 11 1 S SA AT TA A Two Serial ATA SATA ports are available on t...

Page 32: ...connected directly to the Stratix V GX transceiver channels to provide SATA IO connectivity to both host and target devices To verify the functionality of the SATA host device ports a connection can b...

Page 33: ...ferential receive data input after DC blocking capacitor 1 4 V PCML PIN_P1 SATA_DEVICE_TX_n0 Differential transmit data output before DC blocking capacitor 1 4 V PCML PIN_N4 SATA_DEVICE_TX_p0 Differen...

Page 34: ...connected to the Stratix V GX device is a female HSMC connector having a total of 172pins including 121 signal pins 120 signal pins 1 PSNTn pin 39 power pins and 12 ground pins The HSMC connector is...

Page 35: ...can be adjusted by configuring the header position Each port can be individually adjusted to 1 5V 1 8V 2 5V via jumpers on the top right Figure 2 18 depicts the position of the jumpers and their assoc...

Page 36: ...SMC IO Standard Indicators I O Standard Jump Position Jump Position J3 LED Status D25 1 5V J3 1 J3 2 1 8V J3 3 J3 4 2 5V J3 5 J3 6 1 Users who connect a daughter card onto the HSMC ports need to pay c...

Page 37: ...h SW6 If there is no connection established on the HSMC connectors the position 4 of DIP switch SW6 is to set On where the JTAG signals on the HSMC connectors are bypassed illustrated in Figure 2 19 F...

Page 38: ...e 2 21 JTAG Chain Bypassed for HSMC Daughter Card Table 2 22 HSMC Pin Assignments Schematic Signal Names and Functions HSMC Pin Schematic Signal Name Description I O Standard Stratix V GX Pin Number 1...

Page 39: ...Transceiver TX bit 2 1 4 V PCML PIN_J36 22 HSMC_GXB_RX_p2 Transceiver RX bit 2 1 4 V PCML PIN_K38 23 HSMC_GXB_TX_n2 Transceiver TX bit 2n 1 4 V PCML PIN_J37 24 HSMC_GXB_RX_n2 Transceiver RX bit 2n 1 4...

Page 40: ...CIO PIN_E23 77 HSMC_TX_p5 LVDS TX bit 5 or CMOS I O LVDS or VCCIO PIN_P23 78 HSMC_RX_p5 LVDS RX bit 5 or CMOS I O LVDS or VCCIO PIN_B26 79 HSMC_TX_n5 LVDS TX bit 5n or CMOS I O LVDS or VCCIO PIN_N23 8...

Page 41: ...or VCCIO PIN_F30 134 HSMC_RX_n13 LVDS RX bit 13n or CMOS I O LVDS or VCCIO PIN_E25 137 HSMC_TX_p14 LVDS TX bit 14 or CMOS I O LVDS or VCCIO PIN_K31 138 HSMC_RX_p14 LVDS RX bit 14 or CMOS I O LVDS or V...

Page 42: ...Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document...

Page 43: ...according to their design requirements When users complete the settings the System Builder will generate two major files which include top level design file v and the Quartus II setting file qsf The t...

Page 44: ...tion provides the detail procedures on how the System Builder is used Install and launch the System Builder The System Builder is located in the directory Tools SystemBuilder in the System CD Users ca...

Page 45: ...uilder window Select Board Type and Input Project Name Select the target board type and input project name as show in Figure 3 3 Project Name Specify the project name as it is automatically assigned t...

Page 46: ...gnments for some components e g SFP require associated controller codes in the Quartus project otherwise Quartus will result in compilation errors Therefore do not select them if they are not necessar...

Page 47: ...need to dynamically change the frequency they would need to modify the generated control code themselves Figure 3 5 External Programmable Oscillators Project Setting Management The System Builder als...

Page 48: ...y System Builder No Filename Description 1 Project name v Top level Verilog file for Quartus II 2 Si570_controller v Si570 External Oscillator controller IP 3 CDCM6100x_Config v CDCM61004 External Osc...

Page 49: ...s II software to add custom logic into the project and compile the project to generate the SRAM Object File sof For Si570 the Controller will be instantiated in the Quartus II top level file as listed...

Page 50: ...TR5 F40W User Manual 50 www terasic com June 20 2018 If dynamic configuration for the oscillator is required users need to modify the code according to users desired behavior...

Page 51: ...FI flash device Each flash device has a 16 bit data bus and the two combined flash devices allow for a 32 bit flash memory interface For the factory default code to run correctly and update designs in...

Page 52: ...MAX_RST button if board is already powered on 5 When configuration is completed the green Configure Done LED will light If there is error the red Configure Error LED will light 4 4 3 3 F Fl la as sh...

Page 53: ...in the flash_program_bashrc_ub2 file in Figure 4 2 Figure 4 2 Add to these lines to disable elf conversion and programming If your design includes a NIOS II processor and the NIOS II program is stored...

Page 54: ...cated in the CD folder Demonstrations Hello 4 4 4 4 R Re es st to or re e F Fa ac ct to or ry y S Se et tt ti in ng gs s This section describes how to restore the original factory contents to the flas...

Page 55: ...the FACTORY_LOAD dip in SW5 to the upper position 9 Power on the FPGA Board and the Configure Done LED should light Except for programming the Flash with the default code PFL the batch file also write...

Page 56: ...atories advanced DSPLL circuitry to provide a low jitter clock at any frequency The Si570 are user programmable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with 1ppb...

Page 57: ...n program the output frequency through the I2C interface using the following procedure 6 Freeze the DCO bit 4 of Register 137 7 Write the new frequency configuration RFREQ HSDIV and N1 to Register 7 1...

Page 58: ...35 Reference Frequency RST_REG NewFreq Freeze M Freeze VCADC RECALL 137 Reference Frequency Freeze DCO Table 5 2 lists the register settings for some common used frequency Table 5 2 Si570 Register Tab...

Page 59: ...ault output frequency is 100 MHZ Users can change the output frequency by the following control pins 1 PR0 and PR1 2 OD0 OD1 and OD2 3 RSTN 4 CE 5 OS0 and OS1 The following table lists the frequency w...

Page 60: ...nd 1 respectively 5 5 2 2 S Si i5 57 70 0 E Ex xa am mp pl le e R RT TL L In this section we will demonstrate how to use the Terasic Si570 Controller implemented in Verilog to control the Si570 progra...

Page 61: ...2c_bus_controller based on user desired frequency Once i2c_bus_controller receives this data it will transfer these settings to Si570 via serial clock and data bus using I2C protocol The registers in...

Page 62: ...rough an input port named iFREQ_MODE in Si570 controller The specified settings with corresponding frequencies are listed in Table 5 4 For example setting iFREQ_MODE as 3 b110 will configure Si570 to...

Page 63: ...eter For Your Own Frequency If all the six clock frequencies are not desired you can perform the following steps to modify Si570 controller 1 Open i2c_reg_controller v 2 Locate the Verilog code shown...

Page 64: ...new_hs_div 4 b0101 new_n1 8 b0000_0100 fdco 28 h004_E200 end 3 h4 312 5Mhz begin new_hs_div 4 b0100 new_n1 8 b0000_0100 fdco 28 h004_E200 end 3 h5 322 265625Mhz begin new_hs_div 4 b0100 new_n1 8 b000...

Page 65: ...n1 128 For example you want to get a 133 5 mhz clock then fdco 133 5 x 4 x 10 x 64 341760d 0x53700 Find a mode in this RTL code section and modify these three parameters as shown below new_hs_div 3 b1...

Page 66: ...the FPGA configuration finishes users can change settings in Si570_controller v shown below initial_config initial_config iCLK iCLK system clock 50mhz iRST_n iRST_n system reset oINITIAL_START initial...

Page 67: ...us II is installed on your PC Connect the USB Blaster cable to the FGPA board and host PC Install the USB Blaster II driver if necessary According to Table 5 5 the output frequency is determined by se...

Page 68: ...peripheral temperature sensor Si570 and CDCM61004 are all controlled by Nios II through the PIO controller The temperature sensor and external PLL Si570 are controlled through I2C interface The Nios I...

Page 69: ...lock from the external PLL Users can ignore the functionality of the transceiver controller in the demonstration The example uses the CDCM6100x_Config IP which is generated by system builder to progra...

Page 70: ...ed on your PC Power on the FPGA board Use the USB Cable to connect your PC and the FPGA board and install USB Blaster II driver if necessary Execute the demo batch file test_ub2 bat under the batch fi...

Page 71: ...TR5 F40W User Manual 71 www terasic com June 20 2018 Figure 5 8 Temperature Demo Figure 5 9 CDCM 61004 Demo...

Page 72: ...TR5 F40W User Manual 72 www terasic com June 20 2018 Figure 5 10 Si570 Demo...

Page 73: ...HsinChu City 30070 Taiwan 30070 Email support terasic com Web www terasic com TR5 F40W Web TR5 F40W terasic com R Re ev vi is si io on n H Hi is st to or ry y Date Version Changes 2012 7 First publica...

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